Abstract: A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Abstract: Curable silicone compositions, encapsulants including the same, and optical semiconductor devices including the encapsulants are provided herein. In an embodiment, a curable silicone composition includes: (A) an alkenyl group-containing organopolysiloxane having at least two alkenyl groups per molecule; (B) an organohydrogenpolysiloxane having at least two silicon atom-bonded hydrogen atoms per molecule; (C) an epoxy group-containing resinous organopolysiloxane represented by Average Unit Formula (I): (R13SiO1/2)f(R22SiO2/2)g(R1SiO3/2)h(SiO4/2)i(XO1/2)j wherein R1 are independently halogen-substituted or unsubstituted monovalent hydrocarbon groups, at least two R1 are alkenyl groups; R2 are independently halogen-substituted or unsubstituted monovalent hydrocarbon groups or epoxy group-containing organic groups, wherein at least one R2 is an epoxy group-containing organic group; X is a hydrogen atom or an alkyl group; 0?f<1; 0<g<1; 0?h<0.9; 0?i<0.5; and 0<j<0.5; f+g+h+i+j=1.

Abstract: A semiconductor device includes an active pattern on a substrate, source/drain patterns on the active pattern, a plurality of channel layers stacked on the active pattern to be vertically spaced apart from each other and connecting the source/drain patterns with each other, a gate electrode between the source/drain patterns to cross the active pattern and to surround the channel layers, and active contacts at opposite sides of the gate electrode to cover top surfaces of the source/drain patterns. A width of each of the active contacts is smaller than or equal to the largest width of each of the source/drain patterns. Each of the top surfaces of the source/drain patterns has an inclined surface that is inclined relative to a top surface of the substrate, and each of the active contacts includes a protruding portion that protrudes toward the inclined surface.

Abstract: A semiconductor device includes: a drift region of a first conductivity type in a semiconductor body having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; and trenches extending into the semiconductor body from the first main surface and patterning the semiconductor body into mesas. The trenches include: a first trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; a second trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; and a third trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes. Additional semiconductor device embodiments are described herein.

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x?0, and the inner blocking layer including a Si layer.

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Abstract: A semiconductor device includes a gate structure disposed on a substrate; a source and drain layer disposed on the substrate adjacent the gate structure; a first contact plug disposed on the source and drain layer, an insulation pattern structure disposed on the first contact plug, the insulation pattern structure including insulation patterns having different carbon concentrations; and a second contact plug disposed on the gate structure.

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Abstract: An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: A semiconductor structure includes at least a fin structure, a gate structure over the fin structure, a connecting structure, a first dielectric structure over the gate structure, and a second dielectric structure. The fin structure extends in a first direction, and the gate structure extends in a second direction different from the first direction. The connecting structure is disposed over the fin structure and isolated from the gate structure. The second dielectric structure extends in the first direction. The first dielectric structure and the second dielectric structure include a same material. A top surface of the first dielectric structure and a top surface of the second dielectric structure are substantially aligned with each other.

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

Abstract: A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.

Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.

Abstract: A flexible display panel and a flexible array substrate are provided. The flexible display panel includes a flexible base and a thin film transistor. The thin film transistor includes an active layer, and the active layer is arranged on the flexible base. Open pores are formed in the active layer. The open pores penetrate through at least one part of the active layer.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a gate electrode disposed on a substrate. Source/drain regions are disposed on or within the substrate along opposing sides of the gate electrode. A noise reducing component is arranged along an upper surface of the gate electrode and/or along an upper surface of the substrate over the source/drain regions. A cap layer covers the upper surface of the gate electrode and/or the upper surface of the substrate over the source/drain regions. An inter-level dielectric (ILD) is disposed over and along one or more sidewalls of the cap layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.

Abstract: A semiconductor device capable of realizing a capacitative element of which a capacitance value has low bias dependence and of which capacitance density is high without lowering operating voltage is provided. The semiconductor device includes: a semiconductor substrate; a first capacitative element stacked on the semiconductor substrate; and a second capacitative element which is stacked on an opposite side to a side of the semiconductor substrate of the first capacitative element and of which a capacitance value has bias characteristics being opposite to bias characteristics of a capacitance value of the first capacitative element, wherein the first capacitative element and the second capacitative element are connected in parallel.

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

Abstract: A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.