Having Insulated Electrode (e.g., Mosfet, Mos Diode) Patents (Class 257/288)
  • Patent number: 10707167
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 10707300
    Abstract: A semiconductor device having a trench gate structure is provided. A semiconductor device is provided, including: a first-conductivity-type drift region provided in a semiconductor substrate; a first-conductivity-type accumulation region provided above the drift region and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region; and an electric-field relaxation layer provided between the accumulation region and the base region and having a lower doping concentration than the accumulation region. The electric-field relaxation layer may include a first-conductivity-type region including a region having a same doping concentration as the drift region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa, Akio Nakagawa
  • Patent number: 10699957
    Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu, Chanro Park, Laertis Economikos
  • Patent number: 10700177
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Hsiu Hung, Yi-Hsiang Chao, Kuan-Yu Yeh, Kan-Ju Lin, Chun-Wen Nieh, Huang-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 10692776
    Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric R. Miller, Marc Bergendahl, Kangguo Cheng, Yann Mignot
  • Patent number: 10686074
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Tsai, Shahaji B. More, Cheng-Yi Peng, Yu-Ming Lin, Kuo-Feng Yu, Ziwei Fang
  • Patent number: 10685872
    Abstract: A semiconductor device is formed where a conductive extension (e.g., a TS) electrically couples with a first structure (e.g., an S/D) of the semiconductor device, a dielectric is deposited at least on a surface of a second structure (e.g., a gate), where the surface is substantially parallel to a plane of fabrication of the semiconductor device. An insulator cap surrounds an exposed portion of the extension. An opening is formed in the insulator cap, and a first contact (e.g., a CA) is formed through the opening to electrically couple with the first structure. A second contact (e.g., a CB) is formed through an opening in the dielectric at a first portion of the surface and electrically couples with the second structure. The dielectric continues to cover a second portion of the surface, and a portion of the insulator cap is interposed between the first contact and the second contact.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu, Ekmini A. De Silva, Ruilong Xie
  • Patent number: 10685847
    Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 10686075
    Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sheng-Chen Wang, Sai-Hooi Yeong, Yen-Ming Chen, Chi On Chui
  • Patent number: 10679905
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first gate structures on a first region of a substrate, a plurality of second gate structures on a second region of the substrate, and a first stress layer on both sides of each first gate structure; forming a first-region mask layer on the first stress layer; forming a second stress layer on both sides of each second gate structure; forming a contact-hole etch stop layer on the second stress layer; forming a plurality of first contact holes on the first stress layer and a plurality of second contact holes on the second stress layer to expose the contact-hole etch stop layer; at least partially removing the contact-hole etch stop layer in each first contact hole; and removing the first-region mask layer in each first contact hole and the contact-hole etch stop layer in each second contact hole.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10680089
    Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
  • Patent number: 10680084
    Abstract: Epitaxial structures of a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure including two fins, inner and outer fin spacers formed along both sidewalls of the fins, and isolation regions formed around the fins. The FinFET device further includes a gate structure formed over the fin structure and an epitaxial structure formed over the fin structure in a source/drain region. The epitaxial structure is formed by merging the fins with at least one epitaxial semiconductor layer and includes an air gap having a volume determined by the height and separation distance of the inner fin spacers.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 10672764
    Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Seok-hoon Kim, Dong-myoung Kim, Jin-bum Kim, Seung-hun Lee, Cho-eun Lee, Hyun-jung Lee, Sung-uk Jang, Edward Namkyu Cho, Min-hee Choi
  • Patent number: 10672870
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Long-Jie Hong
  • Patent number: 10672768
    Abstract: A method for manufacturing a FinFET having a fin that has a fin body includes selecting a desired electrical performance parameter, selecting a base dimension of the fin, identifying a combination of fin-body doping and fin-geometry that causes the FinFET to have the desired electrical performance parameter, doping the fin body according to the identified fin-body doping, and fabricating the fin according to the fin-geometry.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: June 2, 2020
    Assignee: Tufts University
    Inventors: Brad D. Gaynor, Soha Hassoun
  • Patent number: 10672605
    Abstract: A technique regarding film formation capable of forming a three-dimensional pattern successfully is provided. A film forming method for a processing target object is provided. The processing target object has a supporting base body and a processing target layer. The processing target layer is provided on a main surface of the supporting base body and includes protrusion regions. Each protrusion region is extended upwards from the main surface, and an end surface of each protrusion region is exposed when viewed from above the main surface. The film forming method includes a first process of forming a film on the end surface of each protrusion region; and a second process of selectively exposing one or more end surfaces by anisotropically etching the film formed through the first process.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sho Kumakura, Masahiro Tabata
  • Patent number: 10665718
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 10665700
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu
  • Patent number: 10665688
    Abstract: An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Benjamin Chu-Kung, Van H. Le, Gilbert Dewey, Ashish Agrawal, Jack T. Kavalieros
  • Patent number: 10665511
    Abstract: Embodiments of the invention are directed to a method of forming a protective liner of a semiconductor device, wherein the method includes forming a source or a drain (S/D) region, forming a first layer of protective material over a top surface of the S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material. An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a portion of the second layer of protective material to an oxide of the second type of material, wherein the oxide of the second type of material is the protective liner.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10658288
    Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seul Ki Hong, Heon Jong Shin, Hwi Chan Jun, Min Chan Gwak
  • Patent number: 10658244
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a device region defined by a trench in the substrate. The semiconductor device includes a plurality of fin-shaped active regions spaced apart from each other in the device region and extending in a first direction. The semiconductor device includes a protruding pattern extending along a bottom surface of the trench. Moreover, an interval between the protruding pattern and the plurality of fin-shaped active regions is greater than an interval between two adjacent ones of the plurality of fin-shaped active regions.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Dong-won Kim, Geum-jong Bae
  • Patent number: 10658461
    Abstract: Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Tessera, Inc.
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10658467
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane; a first silicon carbide region of a first conductivity type in the silicon carbide layer; a second silicon carbide region of a second conductivity type between the first silicon carbide region and the first plane; a third silicon carbide region of the second conductivity type between the first silicon carbide region and the first plane, the third silicon carbide region extending in a first direction parallel to the first plane; a first electrode provided on a side of the first plane; a second electrode provided on a side of the second plane; and a metal silicide layer provided between the first electrode and the second silicon carbide region, the metal silicide layer having a portion being in contact with the first plane, and a shape of the portion being an octagon.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 19, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yoichi Hori
  • Patent number: 10651085
    Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole, and forming a conductive structure in the hole.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Jia-Chuan You, Yu-Ming Lin, Chih-Hao Wang, Wai-Yi Lien
  • Patent number: 10644157
    Abstract: Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Andreas Knorr, Srikanth Balaji Samavedam
  • Patent number: 10640621
    Abstract: A membrane for a membrane valve is proposed. The membrane is produced from polytetrafluoroethylene, PTFE. An electronic data carrier is arranged between the membrane and a retaining layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 5, 2020
    Assignee: GEMUE GEBR. MUELLER APPARATEBAU GMBH & CO. KOMMANDITGESELLSCHAFT
    Inventors: Christophe Lebonte, Rolf Meier, Romain Ruocco
  • Patent number: 10644112
    Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Van Le, Seung Hoon Sung, Jack Kavalieros, Ashish Agrawal, Harold Kennel, Siddharth Chouksey, Anand Murthy, Tahir Ghani, Glenn Glass, Cheng-Ying Huang
  • Patent number: 10636894
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Patent number: 10629605
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10629709
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 21, 2020
    Assignee: Tessera, Inc.
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10629628
    Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10629728
    Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; a silicon nitride trench-fill layer disposed in the trench; an interlayer dielectric layer disposed on the silicon nitride trench-fill layer; a working gate striding over the fin structure, on the first side of the trench; a dummy gate striding over the fin structure, on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Patent number: 10629604
    Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun-hee Bai, Myeong-cheol Kim, Kwan-heum Lee, Do-hyoung Kim, Jin-wook Lee, Seung-mo Ha, Dong-Hoon Khang
  • Patent number: 10622356
    Abstract: A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a first metal gate electrode and a second metal gate electrode. The n-channel and the p-channel are made of different materials. The first gate dielectric layer is present on at least opposite sidewalls of the n-channel. The second gate dielectric layer is present on at least opposite sidewalls of the p-channel. The first metal gate electrode is present on the first gate dielectric layer. The second metal gate electrode is present on the second gate dielectric layer. The first metal gate electrode and the second metal gate electrode are made of substantially the same material.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yuan Chang, Xiong-Fei Yu, Hui-Cheng Chang
  • Patent number: 10622379
    Abstract: A semiconductor structure is provided that includes a plurality of high mobility semiconductor material (i.e., silicon germanium alloy of III-V compound semiconductors) fins located above and spaced apart from a bulk semiconductor substrate portion, wherein each of the high mobility semiconductor material fins has a lower faceted surface that is confined within a dielectric isolation structure.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10622463
    Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the silicon germanium of the second portion that is below the gate structure.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Min-Hwa Chi, Jinping Liu
  • Patent number: 10608082
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A semiconductor fin having a channel region, a nanowire arranged over the channel region of the semiconductor fin, a source/drain region connected with the channel region of the semiconductor fin and the nanowire, and a gate structure that overlaps with the channel region of the semiconductor fin and the nanowire. The nanowire has a first gate length, and the channel region of the semiconductor fin has a second gate length that is greater than the first gate length.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie
  • Patent number: 10608034
    Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 31, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Takeshi Ichikawa
  • Patent number: 10608097
    Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 31, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Paul F. Ma, Seshadri Ganguli, Shih Chung Chen, Rajesh Sathiyanarayanan, Atashi Basu, Lin Dong, Naomi Yoshida, Sang Ho Yu, Liqi Wu
  • Patent number: 10606132
    Abstract: The present disclosure relates to a display panel, a display device, and a method for manufacturing a display panel. The display panel has an electrode region, the electrode region including a substrate, a data line layer, and an isolation layer which are provided on the substrate and alternated in a direction parallel to an upper surface of the substrate, wherein the height of the data line layer is equal to the height of the isolation layer. Since there is no height difference between the data line layer and the spacer layer and there is no groove, the possibility that conductive foreign objects are accumulated at the isolation layer at this time is greatly reduced, the smooth surface is more conducive to the movement of foreign objects, and a cleaning tape can remove the foreign objects.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: March 31, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hewei Wang, Lei Han, Peng Jiang, Dong Guo, Nanhong Zhang
  • Patent number: 10607893
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10607896
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: March 31, 2020
    Assignee: IMEC vzw
    Inventors: Lars-Ake Ragnarsson, Hendrik F.W. Dekkers, Tom Schram, Julien Ryckaert, Naoto Horiguchi, Mustafa Badaroglu
  • Patent number: 10600790
    Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: March 24, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Yu-Cheng Tung
  • Patent number: 10600904
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyoshi Kudou, Satoru Tokuda, Satoshi Uchiya
  • Patent number: 10593804
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn
  • Patent number: 10593794
    Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 17, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 10593679
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide (TS) contacts on the semiconductor substrate, recessing the TS contacts to form a gap region, filling the gap region of the recessed TS contacts with a dielectric, selectively etching the gate contacts to form a first conducting layer, and selectively etching the TS contacts to form a second conducting layer.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Sivananda K. Kanakasabapathy, Theodorus E. Standaert, Junli Wang
  • Patent number: 10586740
    Abstract: Method for producing a device provided with FinFET transistors, comprising the following steps: a) making amorphous and doping a first portion of a semiconductor in via a tilted beam oriented toward a first lateral face of the fin, while retaining a first crystalline semiconductor block against a second lateral face of the fin, then b) carrying out at least one recrystallization annealing of said first portion, then c) making amorphous and doping a second portion via a tilted beam oriented toward the second lateral face of the fin, while retaining a second crystalline semiconductor block against said first lateral face of the fin, then d) carrying out at least one recrystallization annealing of the second portion.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 10, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit Mathieu, Perrine Batude