Having Insulated Electrode (e.g., Mosfet, Mos Diode) Patents (Class 257/288)
  • Patent number: 11367815
    Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Bum Han, Young Gil Park, Jung Hwa Park, Na Ri Ahn, Soo Im Jeong, Ki Nam Kim, Moon Sung Kim
  • Patent number: 11362179
    Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm?3 and 1.5×1020 cm?3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 14, 2022
    Inventors: Kiraneswar Muthuseenu, Samuel Anderson, Takeshi Ishiguro
  • Patent number: 11362003
    Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun Lee, Chung-Ting Ko, Chen-Ming Lee, Mei-Yun Wang, Fu-Kai Yang
  • Patent number: 11362199
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Hsieh Wong, Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11355601
    Abstract: A semiconductor structure includes a source feature, a drain feature, one or more channel layers connecting the source feature and the drain feature, and a gate structure between the source feature and the drain feature. The gate structure engages each of the one or more channel layers. The semiconductor structure further includes a first source silicide feature over the source feature, a source contact over the first source silicide feature, a second source silicide feature under the source feature, a via under the second source silicide feature, and a power rail under the via. The first and the second source silicide features fully surround the source feature in a cross-sectional view. The power rail is a backside power rail.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang, Cheng-Chi Chuang
  • Patent number: 11342444
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
  • Patent number: 11335710
    Abstract: A thin film transistor, a display panel and a preparation method thereof and a display apparatus are provided. The thin film transistor includes: a substrate; a gate metal located on a side of the substrate; a gate insulating layer located on a side of the gate metal away from the substrate; an active layer located on a side of the gate insulating layer away from the substrate; a first metal oxide and a second metal oxide which are located on a side of the active layer away from the substrate and are arranged on a same layer; and a source metal and a drain metal which are located on sides of the first metal oxide and the second metal oxide away from the substrate and are arranged in a same layer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 17, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Qinghe Wang, Tongshang Su, Yongchao Huang, Yingbin Hu, Yang Zhang, Haitao Wang, Ning Liu, Guangyao Li, Zheng Wang, Yu Ji, Jinliang Hu, Wei Song, Jun Cheng, Liangchen Yan
  • Patent number: 11329045
    Abstract: A field effect transistor structure includes a connection hole leading out a gate structure arranged on the formation area of one of a plurality of fins, and connection holes leading out a source electrode and a drain electrode, wherein the connection hole leading out the gate structure is located on formation areas of different fins; a gate cap layer formed at the top of the gate structure formed on the same fin body and adjacent to the connection holes leading out the source electrode and the drain electrode, wherein the gate cap layer protects the corresponding gate structure; buried holes formed on the source electrode and the drain electrode at both sides of the connection hole leading out the gate structure; a buried hole cap layer formed on the buried holes, and the buried hole cap layer protects the buried holes connecting the source and the drain electrode.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 10, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventor: Wenyin Weng
  • Patent number: 11329138
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Christopher Kenyon, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu, Szuya S. Liao, Walid M. Hafez
  • Patent number: 11327344
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 10, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11315921
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, Tzu-Wei Lin, Ju Ru Hsieh, Ching-Lun Lai, Ming-Kai Lo
  • Patent number: 11316037
    Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 26, 2022
    Assignee: Silanna Asia Pte Ltd
    Inventors: Vadim Kushner, Nima Beikae
  • Patent number: 11309189
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 11302818
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Patent number: 11302802
    Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Heng Wang, Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11302623
    Abstract: An electronic device includes a first metal plate including a first wiring and a second wiring, an electronic component mounted on a lower surface of the first wiring so as to overlap the second wiring in plan view, a second metal plate including an electrode electrically connected to the lower surface of the first wiring, and an insulation layer filling a space between the first metal plate, the second metal plate, and the electronic component and covering the electronic component. The upper surface of the second wiring is exposed from the insulation layer.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 12, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Tadaaki Katsuyama
  • Patent number: 11302787
    Abstract: A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Syuan Ciou, Hui-Zhong Zhuang, Jung-Chan Yang, Li-Chun Tien
  • Patent number: 11302790
    Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar
  • Patent number: 11282749
    Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11276755
    Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 11276768
    Abstract: A semiconductor device including a structure having N gate electrode layers G and (N?1) channel formation region layers CH (where N?3) alternately juxtaposed on an insulating material layer formed on a surface of a conductive substrate. Each of the structure, the channel formation region layer CH, and the gate electrode layer G has a bottom surface, a top surface, and four side surfaces. A second surface of the nth channel formation region layer is connected to a fourth surface of the nth gate electrode layer. A fourth surface of the nth channel formation region layer is connected to a second surface of the (n+1)th gate electrode layer. One of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 15, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuzo Fukuzaki, Koji Fukumoto
  • Patent number: 11270888
    Abstract: A device includes a source/drain (S/D) in a substrate and adjacent to a gate structure, wherein the S/D comprises a protrusion extending from a top surface of the S/D, and the protrusion has a tapered profile. The device further includes a contact plug electrically connected to the protrusion.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Keng-Chuan Chang, Ting-Siang Su
  • Patent number: 11264512
    Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Aaron Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani, Willy Rachmady, Rishabh Mehandru, Nazila Haratipour, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Shriram Shivaraman
  • Patent number: 11264383
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 11264393
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11264483
    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure, the semiconductor structure including: a fin structure; a dummy gate across over the fin structure to define a channel region of the fin structure; and a dummy dielectric layer separating the channel region of the fin structure from the dummy gate; removing the dummy gate and the dummy dielectric layer to expose the channel region of the fin structure; and forming a doped interfacial layer covering the channel region of the fin structure, in which the doped interfacial layer includes a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Cheng-Hsien Wu
  • Patent number: 11257911
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11257769
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes: a first active region having a first plurality of field effect transistors (FETs); and an interconnect contacting sources and drains of the first plurality of FETs in the first active region through a first set of contact structures. At least one of the first set of contact structures is electrically non-conductive.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11251306
    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 15, 2022
    Inventors: Deokhan Bae, Juhun Park, Myungyoon Um, Kwangyong Jang
  • Patent number: 11251036
    Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 15, 2022
    Assignee: IMEC vzw
    Inventors: Shairfe Muhammad Salahuddin, Alessio Spessot
  • Patent number: 11244832
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
  • Patent number: 11244866
    Abstract: In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Tse Hung, Chao-Ching Cheng, Tse-An Chen, Hung-Li Chiang, Lain-Jong Li, Tzu-Chiang Chen
  • Patent number: 11245861
    Abstract: Stability of a current-voltage conversion circuit is increased in a solid-state imaging element that converts photocurrent to a voltage signal. A photodiode photoelectrically converts incident light and generates photocurrent. A conversion transistor converts photocurrent to a voltage signal and outputs the voltage signal from a gate. A current source transistor supplies predetermined constant current to an output signal line connected to the gate. A voltage supply transistor supplies a certain voltage corresponding to the predetermined constant current from the output signal line to a source of the conversion transistor. A capacitance is connected between the gate and the source of the conversion transistor.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 8, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsumi Niwa
  • Patent number: 11239367
    Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Chih Chieh Yeh, Cheng-Hsien Wu
  • Patent number: 11239110
    Abstract: Semiconductor structure and method for forming semiconductor structure are provided. A substrate is provided, including a first dielectric layer, a first conductive layer and a second conductive layer. A first stop layer is formed on a top surface of the first conductive layer and a top surface of the second conductive layer, and a second stop layer is formed on a surface of the first dielectric layer. A second dielectric layer is formed on a surface of the first stop layer and a surface of the second stop layer. A first opening and a second opening are formed in the second dielectric layer by etching a portion of the second dielectric layer until the surface of the first stop layer is exposed. The first opening exposes the first stop layer on the first conductive layer, and the second opening exposes the first stop layer on the second conductive layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jiquan Liu
  • Patent number: 11239311
    Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hui-Jung Kim, Kyu Jin Kim, Sang-Il Han, Kyu Hyun Lee, Woo Young Choi, Yoo Sang Hwang
  • Patent number: 11233071
    Abstract: An electrode structure which includes a copper metal layer formed on a substrate, wherein the copper metal layer doped with a first metal ion within a first depth from upper surface, the first metal ion and the copper grain forming a copper alloy layer; the first depth being less than thickness of the copper metal layer, and the first metal ion being a metal ion having corrosion resistance and an ionic radius smaller than a gap between copper grains.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 25, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaobo Hu
  • Patent number: 11233054
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, which includes a first region, a second region, and a third region. The semiconductor structure also includes a first fin, a second fin, and a third fin formed on the first, second, and third regions, respectively. Moreover, the semiconductor structure includes an isolation layer formed on the substrate, and a portion of sidewall surface of each of the first, second, and third fins. In addition, the semiconductor structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer formed on the first, second, and third fins, respectively. Two sides of the third epitaxial layer are in contact with the first epitaxial layer and the second epitaxial layer, respectively. Further, the semiconductor structure includes a conductive structure formed on the first, second, and third epitaxial layers.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11211490
    Abstract: A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 28, 2021
    Inventors: Sun Hom Paak, Sung Min Kim
  • Patent number: 11211494
    Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myung Ok Kim
  • Patent number: 11211295
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes providing a substrate having a fin extending from the substrate. An in-situ doped layer is formed on the fin. By way of example, the in-situ doped layer may include an in-situ doped well region formed by an epitaxial growth process. In some examples, the in-situ doped well region includes an N-well or a P-well region. After formation of the in-situ doped layer on the fin, an undoped layer is formed on the in-situ doped layer, and a gate stack is formed over the undoped layer. The undoped layer may include an undoped channel region formed by an epitaxial growth process. In various examples, a source region and a drain region are formed adjacent to and on either side of the undoped channel region.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu
  • Patent number: 11211462
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, ChoongHyun Lee, Kangguo Cheng, Ruilong Xie
  • Patent number: 11212470
    Abstract: The invention relates to pixel circuit and an operating method thereof, comprising—a front-end circuit (1) comprising a single photodiode (PD) and having an output (4), said front-end circuit (1) being configured for delivering on said output a photoreceptor signal derived from a light exposure of said single photodiode (PD);—a transient detector circuit (2) configured for detecting a change in said photoreceptor signal delivered on said output (4);—an exposure measurement circuit (3) configured for measuring said photoreceptor signal delivered on said output (4) upon detection by the transient detector circuit (2) of a change in the photoreceptor signal.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Prophesee
    Inventors: Daniel Matolin, Christoph Posch
  • Patent number: 11205724
    Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sheng-Chen Wang, Sai-Hooi Yeong, Yen-Ming Chen, Chi On Chui
  • Patent number: 11201244
    Abstract: Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Babar Khan, Arvind Kumar, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 11201245
    Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOD metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: December 14, 2021
    Assignee: pSemi Corporation
    Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener, Alexander Dribinsky, Tae-Youn Kim
  • Patent number: 11201215
    Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 14, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja, Zvi Or-Bach, Dinesh Maheshwari
  • Patent number: 11195762
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • Patent number: 11189616
    Abstract: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Koji Watanabe
  • Patent number: 11189490
    Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Georgios Vellianitis