With Means To Localize Region Of Conduction (e.g., "pore" Structure) Patents (Class 257/3)
  • Patent number: 11522010
    Abstract: A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprises providing a base structure including BiCMOS circuitry on a semiconductor substrate, and forming on the base structure a dielectric contact window layer having metal through-plugs that contact the BiCMOS circuitry. The method includes constructing the PCS on the contact window layer. The PCS includes: a phase change region, between ohmic contacts on the phase change region, to operate as a switch controlled by heat. The method further includes forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers that interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides connections to a second of the ohmic contacts and to the resistive heater.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 6, 2022
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Patrick B. Shea, Robert M. Young, Keith H. Chung, Andris Ezis, Ishan Wathuthanthri
  • Patent number: 11508436
    Abstract: A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignees: Sharp Semiconductor Innovation Corporation, TOHOKU UNIVERSITY
    Inventors: Yoshihisa Sekiguchi, Tetsuo Endoh
  • Patent number: 11469139
    Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Patent number: 11442296
    Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Feng-Wei Kuo, Min-Hsiang Hsu, Lan-Chou Cho, Chewn-Pu Jou, Wen-Shiang Liao
  • Patent number: 11417705
    Abstract: A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Prashant Majhi, Elijah Karpov, Ravi Pillarisetty, Ashishek Sharma
  • Patent number: 11411177
    Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 9, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
  • Patent number: 11410722
    Abstract: A phase-change memory device and a dynamic resistance drift compensation method thereof are provided. The phase-change memory device includes a plurality of bit lines; a plurality of source lines crossing the plurality of bit lines; a plurality of memory cells at respective intersections between the plurality of bit lines and the plurality of source lines, the plurality of memory cells each including a phase-change layer; a current generator connected to the plurality of bit lines and configured to generate a set current to be supplied to each of the plurality of memory cells; and a control driver configured to control the current generator and the plurality of bit lines to supply the set current to each of the plurality of memory cells.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunheub Song, Yoonseong Choi
  • Patent number: 11404480
    Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Lin, Kuo-Chyuan Tzeng, Kao-Chao Lin, Chang-Chih Huang
  • Patent number: 11404633
    Abstract: Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: William J. Gallagher
  • Patent number: 11362031
    Abstract: An integrated circuit device includes a conductive line including a metal layer and an insulation capping structure covering the conductive line. The first insulation capping structure includes a first insulation capping pattern that is adjacent to the metal layer in the insulation capping structure and has a first density, and a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween and having a second density that is greater than the first density. In order to manufacture the integrated circuit device, the conductive line having a metal layer is formed on a substrate, a first insulation capping layer having the first density is formed directly on the metal layer, and a second insulation capping layer having the second density that is greater than the first density is formed on the first insulation capping layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 14, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choonghyun Lee, Joonyong Choe, Youngju Lee
  • Patent number: 11355549
    Abstract: A light emitting diode (LED) may include a conductive via in a first portion of an epitaxial layer and a first contact on a second portion of the epitaxial layer. The first portion and the second portion may be separated by an isolation region. The LED may include a transparent conductive layer on the epitaxial layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 7, 2022
    Assignee: LUMILEDS LLC
    Inventors: Frederic Stephane Diana, Alan Andrew McReynolds
  • Patent number: 11289649
    Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 29, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Lup San Leong, Curtis Chun-I Hsieh, Juan Boon Tan, Eng Huat Toh, Kin Wai Tang
  • Patent number: 11258023
    Abstract: A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: February 22, 2022
    Assignee: Nantero, Inc.
    Inventors: Mark Ramsbey, Thomas Rueckes, Tatsuya Yamaguchi, Syuji Nozawa, Nagisa Sato
  • Patent number: 11223013
    Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 11, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qi Liu, Xiaolong Zhao, Sen Liu, Ming Liu, Hangbing Lv, Shibing Long, Yan Wang, Facai Wu
  • Patent number: 11211427
    Abstract: A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinwoo Lee, Zhe Wu, Kyubong Jung, Seung-geun Yu, Ja Bin Lee
  • Patent number: 11205117
    Abstract: Neuromorphic devices are described. A neuromorphic device may include a pre-synaptic neuron; row lines extending from the pre-synaptic neuron in a first direction; a post-synapse neuron; a column line extending from the post-synaptic neuron in a second direction perpendicular to the first direction; and synapses disposed in intersection regions between the row lines and the column line. The synapses may include a first synapse having a first memristor; and a second synapse having a first selection device and a second memristor.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 21, 2021
    Assignee: SK HYNIX INC.
    Inventor: Seong-Hyun Kim
  • Patent number: 11201193
    Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: December 14, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Xia Li, Gengming Tao
  • Patent number: 11193836
    Abstract: The invention relates to a strain gage and methods for making and using the same to measure strain of a surface of interest. In particular, the invention relates to a semiconductor strain gage held by a metal body using a ceramic interface between the gage and the body, which that can be attached to a surface of interest. The invention also relates to methods for making the ceramic interface and attaching the semiconductor strain gage to a surface of interest. The invention, including its various embodiments, also relates to using the semiconductor strain gage to measure strain at temperatures above 1000° F.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 7, 2021
    Inventors: Stanley Timothy Rosinski, Christopher Adam Suprock, Joseph James Christian
  • Patent number: 11127896
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 21, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Frederick Mancoff, Sumio Ikegawa
  • Patent number: 11127793
    Abstract: A manufacturing method of a three-dimensional vertical memory (3D-MV) includes the steps of: (A) forming a stack of interleaved lightly-doped layers and insulating layers; and, (B) a first photolithography step and an ion-implant step to form first and second regions in each lightly-doped layer. The first region, disposed around and shared by a plurality of memory holes, has a higher resistivity than the second region.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: September 21, 2021
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 11050018
    Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.
    Type: Grant
    Filed: October 26, 2019
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai, Chung-Ju Lee
  • Patent number: 11038108
    Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
  • Patent number: 11011227
    Abstract: Methods, systems and devices for operation of non-volatile memory device are described herein. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the non-volatile memory element.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 18, 2021
    Assignee: ARM Ltd.
    Inventors: Supreet Jeloka, Shidhartha Das, Mudit Bhargava, Saurabh Pijuskumar Sinha, James Edwards Myers
  • Patent number: 10985316
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yang Chen, Chun-Yang Tsai, Kuo-Ching Huang, Wen-Ting Chu, Pili Huang, Cheng-Jun Wu
  • Patent number: 10903422
    Abstract: A method for fabricating a semiconductor device including a vertically oriented memory structure includes forming at least one pillar including phase-change memory (PCM) material on at least one electrode, forming a plurality of spacers on the electrode and along sidewalls of the pillar, and forming, by processing the plurality of spacers and the pillar, a modified pillar having a vertically oriented dumbbell shape associated with a vertically oriented PCM memory structure.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10886221
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Takaco Umezawa
  • Patent number: 10879463
    Abstract: A phase change memory (PCM) cell with enhanced thermal isolation and low power consumption is provided. In some embodiments, the PCM cell comprises a bottom electrode, a dielectric layer, a heating element, and a phase change element. The dielectric layer is on the bottom electrode. The heating element extends through the dielectric layer, from a top of the dielectric layer to the bottom electrode. Further, the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity. The phase change element overlies and contacts the heating element. An interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element. Also provided is a method for manufacturing the PCM cell.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi Jen Tsai, Shih-Chang Liu
  • Patent number: 10879459
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10861902
    Abstract: A semiconductor device includes first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.
    Type: Grant
    Filed: June 16, 2018
    Date of Patent: December 8, 2020
    Inventors: Kilho Lee, Gwanhyeob Koh, Ilmok Park, Junhee Lim
  • Patent number: 10840447
    Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim, Barry Linder
  • Patent number: 10812033
    Abstract: Various embodiments include an apparatus to filter radio-frequencies in a plasma-based processing device. In various embodiments, an RF filter device includes a number of substantially-planar spiral-filters electrically coupled to and substantially parallel to each other in a spaced-apart arrangement. In one embodiment, each of the planar spiral-filters is coupled to an adjacent one of the planar spiral filters as either an inside-to-inside electrical connection or an outside-to-outside electrical connection based on an arrangement of the successive spirals so as to increase a total value of inductance. Other methods, devices, apparatuses, and systems are disclosed.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 20, 2020
    Assignee: Lam Research Corporation
    Inventors: Sean Kelly O'Brien, Seyed Jafar Jafarian-Tehrani, Hema Swaroop Mopidevi, Neil Martin Paul Benjamin, Jason Augustino
  • Patent number: 10811604
    Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode separated from the first electrode, a resistive-change material layer provided between the first electrode and the second electrode and configured to store information due to a resistance change caused by an electrical signal applied through the first electrode and the second electrode, and a diffusion prevention layer provided between the first electrode and the resistive-change material layer and/or between the second electrode and the resistive-change material layer and including a two-dimensional (2D) material having a monolayer thickness of about 0.35 nm or less.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 20, 2020
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Minhyun Lee, Seongjun Park, Hyunjae Song, Hyeonjin Shin, Kibum Kim, Sanghun Lee, Yunho Kang
  • Patent number: 10777739
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10770656
    Abstract: Method(s) and apparatuses for forming a phase change memory. A method includes: forming a crystalline phase-change layer at a first position in along a surface of a first semiconductor layer, and forming an amorphous phase-change layer at a second position along the surface of a second semiconductor layer, wherein the crystalline phase-change layer and the amorphous phase-change layer are in contact.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gloria Wing Yun Fraczak, Matthew Brightsky, Chung Hon Lam, Fabio Carta, Robert Bruce, Takeshi Masuda, Koukou Suu
  • Patent number: 10727277
    Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yosuke Murakami, Takeshi Ishizaki, Yusuke Arayashiki, Kazuhiko Yamamoto, Kana Hirayama
  • Patent number: 10720580
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contacts formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10714684
    Abstract: A PCM cell is provided that includes a phase change memory material that is sandwiched between top and bottom electrodes which are both composed of a doped silicon germanium alloy. A doped silicon germanium alloy has good electrical conductivity, while having a lower thermal conductivity than conventional conductive materials such as TiN or W that are typically used in PCM cells. The presence of the doped silicon germanium alloy mitigates heat loss in the PCM cell thus reducing reset current and, in some embodiments, thermal cross-talk between adjacent PCM cells. Further reduction of heat loss can be obtained by providing an airgap-containing dielectric spacer laterally adjacent to the PCM cell.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10707416
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 7, 2020
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Jun Liu, Kristy A. Campbell
  • Patent number: 10693062
    Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 23, 2020
    Assignee: Crossbar, Inc.
    Inventors: Sundar Narayanan, Sung Hyun Jo, Liang Zhao
  • Patent number: 10680171
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 9, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 10680066
    Abstract: Example embodiments relate to a graphene device, methods of manufacturing and operating the same, and an electronic apparatus including the graphene device. The graphene device is a multifunctional device. The graphene device may include a graphene layer and a functional material layer. The graphene device may have a function of at least one of a memory device, a piezoelectric device, and an optoelectronic device within the structure of a switching device/electronic device. The functional material layer may include at least one of a resistance change material, a phase change material, a ferroelectric material, a multiferroic material, multistable molecules, a piezoelectric material, a light emission material, and a photoactive material.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Kiyoung Lee, Seongjun Park
  • Patent number: 10665818
    Abstract: Provided are an encapsulation structure, a method for producing the same, and a display apparatus. The encapsulation structure comprising a plurality of layers covering the outside of a device to be encapsulated, wherein the plurality of layers comprises an inorganic layer and an organic layer, which are stacked alternatively, wherein the organic layer comprises an organic layer matrix and hydrophobic particles, and wherein the hydrophobic particle comprises an inorganic nanoparticle and a hydrophobic group.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 26, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bo Jiang, Wei Xu, Wei Huang
  • Patent number: 10636966
    Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Boniardi, Andrea Redaelli
  • Patent number: 10636552
    Abstract: The present invention relates to a multi-function electronic device having a memristor and a memcapacitor and a method for manufacturing the same. The multi-function electronic device having a memristor and a memcapacitor has a laminated structure of a first insulating layer comprising an organic material/an active layer/a second insulating layer comprising an organic material, and thus has a resistance and capacitance varying with the applied voltage.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 28, 2020
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Moon Ho Ham, Myung Woo Son, Yun Bin Jeong
  • Patent number: 10622551
    Abstract: A method for forming a semiconductor device is provided. The method includes: providing a semiconductor substrate; forming a bottom electrode layer over the semiconductor substrate; forming a magnetic tunneling junction (MTJ) layer over the bottom electrode layer; forming a top electrode layer over the MTJ layer; and performing a single etch operation to etch the bottom electrode layer, the MTJ layer, and the top electrode layer, thereby forming a bottom electrode, a MTJ, and a top electrode respectively.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10622555
    Abstract: A phase change memory (PCM) device including a PCM structure with a getter metal layer disposed between a phase change element (PCE) and a dielectric layer is provided. The PCM structure includes a dielectric layer, a bottom electrode, a via, a PCE, and a getter metal layer. The dielectric layer is disposed over a substrate. The bottom electrode overlies the dielectric layer. The via extends through the dielectric layer, from a bottom surface of the dielectric layer to a top surface of the dielectric layer. The phase change element overlies the bottom electrode. The getter metal layer is disposed between the dielectric layer and the PCE.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Chin-Wei Liang, Hsing-Lien Lin, Fa-Shen Jiang
  • Patent number: 10622562
    Abstract: An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthew J. BrightSky
  • Patent number: 10566531
    Abstract: An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthew J. BrightSky
  • Patent number: 10566388
    Abstract: In a shared three-dimensional vertical memory (3D-MV), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 18, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10559752
    Abstract: A semiconductor device includes a first word line and a first bit line. The semiconductor device further includes a mold film disposed between the first word line and the first bit line, and a first memory cell disposed in the mold film. The first memory cell includes a first lower electrode in contact with the first word line. Side surfaces of the first lower electrode are in direct contact with the mold film. The first memory cell includes a first phase-change memory in contact with the first lower electrode, a first intermediate electrode in contact with the first phase-change memory, a first ovonic threshold switch (OTS) in contact with the first intermediate electrode, and a first upper electrode disposed between the first OTS and the first bit line, the first upper electrode in contact with the first OTS and the first bit line.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il Mok Park, Tae Jin Park