With Means To Localize Region Of Conduction (e.g., "pore" Structure) Patents (Class 257/3)
-
Patent number: 12108692Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.Type: GrantFiled: September 13, 2021Date of Patent: October 1, 2024Assignee: International Business Machines CorporationInventors: Heng Wu, Tian Shen, Kevin W. Brew, Jingyun Zhang
-
Patent number: 12074108Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.Type: GrantFiled: October 6, 2023Date of Patent: August 27, 2024Assignee: Kioxia CorporationInventor: Takaco Umezawa
-
Patent number: 12041860Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.Type: GrantFiled: January 21, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Wen-Zhang Lin, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Chrong-Jung Lin, Ya-Chin King, Cheng-Jun Lin, Wang-Yi Lee
-
Patent number: 11996145Abstract: Technology is disclosed for a memory system having a cross-point array with threshold switching selector memory cells. Each memory cell has a two-terminal threshold switching selector memory element that may be programmed to two different on-state conductances in order to store information. One bit value may be represented by a high-resistance state (HRS) when in the on-state and another bit value may be represented by a low-resistance state (LRS) when in the on-state. In one aspect, a conditioning signal is applied to the memory cell prior to programming. Applying a program signal with the opposite polarity as the conditioning signal may result in a higher conductance in the on-state than applying a program signal with the same polarity as the conditioning signal. The memory element may also serve as a selector for the memory cell. The memory element may include an Ovonic Threshold Switch (OTS).Type: GrantFiled: May 3, 2022Date of Patent: May 28, 2024Assignee: Western Digital Technologies, Inc.Inventors: Hans Jurgen Richter, Michael K. Grobis
-
Patent number: 11996464Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.Type: GrantFiled: May 11, 2022Date of Patent: May 28, 2024Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., JIANGSU ADVANCED MEMORY SEMICONDUCTOR CO., LTD.Inventors: Chieh-Fang Chen, Kuo-Feng Lo, Chung-Hon Lam, Yu Zhu
-
Patent number: 11985909Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.Type: GrantFiled: June 10, 2019Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Elijah Karpov, Mauro Kobrinsky
-
Patent number: 11963469Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.Type: GrantFiled: May 15, 2023Date of Patent: April 16, 2024Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ruilong Xie, Carl Radens, Juntao Li
-
Patent number: 11963465Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.Type: GrantFiled: February 27, 2023Date of Patent: April 16, 2024Assignee: Hefei Reliance Memory LimitedInventors: Zhichao Lu, Gary Bela Bronner
-
Patent number: 11957067Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: GrantFiled: May 24, 2021Date of Patent: April 9, 2024Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Simon Jeannot
-
Patent number: 11916019Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.Type: GrantFiled: January 24, 2022Date of Patent: February 27, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Te-Yin Chen
-
Patent number: 11871574Abstract: A semiconductor memory device according to an embodiment includes: a first interlayer insulating layer and a second interlayer insulating layer that are arranged in a first direction; a gate electrode layer provided between the first interlayer insulating layer and the second interlayer insulating layer; a semiconductor layer extending in the first direction and facing the gate electrode layer in a second direction intersecting the first direction; a first insulating layer provided between the gate electrode layer and the semiconductor layer; a charge storage layer provided between the gate electrode layer and the first insulating layer and containing a metal element; a second insulating layer provided between the gate electrode layer and the charge storage layer; and a first region provided between the charge storage layer and the first insulating layer and containing manganese (Mn), silicon (Si), and oxygen (O).Type: GrantFiled: September 10, 2021Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Atsushi Murakoshi, Tomoya Kawai
-
Patent number: 11856868Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: GrantFiled: May 3, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-Yao Chen, Chun-Heng Liao, Hung Cho Wang
-
Patent number: 11832538Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.Type: GrantFiled: September 7, 2021Date of Patent: November 28, 2023Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Curtis Chun-I Hsieh, Juan Boon Tan, Calvin Lee
-
Patent number: 11817400Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.Type: GrantFiled: July 15, 2021Date of Patent: November 14, 2023Assignee: Psiquantum, Corp.Inventors: Yong Liang, Vimal Kumar Kamineni, Chia-Ming Chang, James McMahon
-
Patent number: 11818969Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.Type: GrantFiled: November 13, 2020Date of Patent: November 14, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Jianxun Sun, Juan Boon Tan, Tupei Chen
-
Patent number: 11805714Abstract: Methods and structures for fabricating a semiconductor device that includes a reduced programming current phase change memory (PCM) are provided. The method includes forming a bottom electrode. The method further includes forming a PCM and forming a conductive bridge filament in a dielectric to serve as a heater for the PCM. The method also includes forming a top electrode.Type: GrantFiled: August 4, 2021Date of Patent: October 31, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nanbo Gong, Takashi Ando, Guy M. Cohen
-
Patent number: 11800819Abstract: A non-volatile memory structure may include a phase change memory comprising a phase change material. The non-volatile memory structure may include a Schottky diode in series with the phase change memory, wherein a Schottky barrier of the Schottky diode is a surface of the phase change memory. This may be accomplished through a proper selection of materials for the contact of the phase change memory. This may create an integrated diode-memory structure which may control directionality of current without a penalty on the footprint of the structure.Type: GrantFiled: December 1, 2020Date of Patent: October 24, 2023Assignee: International Business Machines CorporationInventors: Timothy Mathew Philip, Kevin W. Brew, Lawrence A. Clevenger
-
Patent number: 11678594Abstract: According to one embodiment, the semiconductor storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, a first semiconductor device extending in a third direction intersecting the first direction and the second direction, connected to the first wiring and the second wiring, and including a first selector layer and a first variable resistance layer, a first insulator extending in the second and third directions and adjacent to the first semiconductor device in the first direction, and a second insulator extending in the second and third directions and including an air gap disposed between the first semiconductor device and the first insulator.Type: GrantFiled: March 3, 2021Date of Patent: June 13, 2023Assignee: KIOXIA CORPORATIONInventor: Natsuumi Takahashi
-
Patent number: 11647639Abstract: A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.Type: GrantFiled: February 9, 2022Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Takashi Ando, Hiroyuki Miyazoe
-
Patent number: 11647681Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.Type: GrantFiled: October 1, 2020Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim, Barry Linder
-
Patent number: 11647680Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.Type: GrantFiled: June 11, 2020Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Takashi Ando, Hiroyuki Miyazoe, Eduard Albert Cartier, Babar Khan, Youngseok Kim, Dexin Kong, Soon-Cheon Seo, Joel P. De Souza
-
Patent number: 11635643Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.Type: GrantFiled: August 8, 2022Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Huan-Neng Chen, Feng-Wei KUo, Min-Hsiang Hsu, Lan-Chou Cho, Chewn-Pu Jou, Wen-Shiang Liao
-
Patent number: 11631810Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.Type: GrantFiled: April 19, 2021Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yang Chen, Chun-Yang Tsai, Kuo-Ching Huang, Wen-Ting Chu, Pili Huang, Cheng-Jun Wu
-
Patent number: 11575019Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.Type: GrantFiled: August 28, 2019Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Kyun An, Dong Hyun Im
-
Patent number: 11569445Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.Type: GrantFiled: January 29, 2021Date of Patent: January 31, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee
-
Patent number: 11522010Abstract: A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprises providing a base structure including BiCMOS circuitry on a semiconductor substrate, and forming on the base structure a dielectric contact window layer having metal through-plugs that contact the BiCMOS circuitry. The method includes constructing the PCS on the contact window layer. The PCS includes: a phase change region, between ohmic contacts on the phase change region, to operate as a switch controlled by heat. The method further includes forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers that interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides connections to a second of the ohmic contacts and to the resistive heater.Type: GrantFiled: August 19, 2019Date of Patent: December 6, 2022Assignee: Northrop Grumman Systems CorporationInventors: Patrick B. Shea, Robert M. Young, Keith H. Chung, Andris Ezis, Ishan Wathuthanthri
-
Patent number: 11508436Abstract: A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation.Type: GrantFiled: September 29, 2020Date of Patent: November 22, 2022Assignees: Sharp Semiconductor Innovation Corporation, TOHOKU UNIVERSITYInventors: Yoshihisa Sekiguchi, Tetsuo Endoh
-
Patent number: 11469139Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.Type: GrantFiled: January 9, 2020Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Yu Chen, Chung-Liang Cheng
-
Patent number: 11442296Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.Type: GrantFiled: July 20, 2020Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Huan-Neng Chen, Feng-Wei Kuo, Min-Hsiang Hsu, Lan-Chou Cho, Chewn-Pu Jou, Wen-Shiang Liao
-
Patent number: 11417705Abstract: A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.Type: GrantFiled: September 28, 2018Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Brian Doyle, Prashant Majhi, Elijah Karpov, Ravi Pillarisetty, Ashishek Sharma
-
Patent number: 11411177Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: GrantFiled: May 20, 2020Date of Patent: August 9, 2022Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
-
Patent number: 11410722Abstract: A phase-change memory device and a dynamic resistance drift compensation method thereof are provided. The phase-change memory device includes a plurality of bit lines; a plurality of source lines crossing the plurality of bit lines; a plurality of memory cells at respective intersections between the plurality of bit lines and the plurality of source lines, the plurality of memory cells each including a phase-change layer; a current generator connected to the plurality of bit lines and configured to generate a set current to be supplied to each of the plurality of memory cells; and a control driver configured to control the current generator and the plurality of bit lines to supply the set current to each of the plurality of memory cells.Type: GrantFiled: October 21, 2020Date of Patent: August 9, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yunheub Song, Yoonseong Choi
-
Patent number: 11404480Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.Type: GrantFiled: December 26, 2019Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tzu Lin, Kuo-Chyuan Tzeng, Kao-Chao Lin, Chang-Chih Huang
-
Patent number: 11404633Abstract: Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.Type: GrantFiled: March 23, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: William J. Gallagher
-
Patent number: 11362031Abstract: An integrated circuit device includes a conductive line including a metal layer and an insulation capping structure covering the conductive line. The first insulation capping structure includes a first insulation capping pattern that is adjacent to the metal layer in the insulation capping structure and has a first density, and a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween and having a second density that is greater than the first density. In order to manufacture the integrated circuit device, the conductive line having a metal layer is formed on a substrate, a first insulation capping layer having the first density is formed directly on the metal layer, and a second insulation capping layer having the second density that is greater than the first density is formed on the first insulation capping layer.Type: GrantFiled: March 5, 2020Date of Patent: June 14, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choonghyun Lee, Joonyong Choe, Youngju Lee
-
Patent number: 11355549Abstract: A light emitting diode (LED) may include a conductive via in a first portion of an epitaxial layer and a first contact on a second portion of the epitaxial layer. The first portion and the second portion may be separated by an isolation region. The LED may include a transparent conductive layer on the epitaxial layer.Type: GrantFiled: December 21, 2018Date of Patent: June 7, 2022Assignee: LUMILEDS LLCInventors: Frederic Stephane Diana, Alan Andrew McReynolds
-
Patent number: 11289649Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.Type: GrantFiled: April 13, 2020Date of Patent: March 29, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Lup San Leong, Curtis Chun-I Hsieh, Juan Boon Tan, Eng Huat Toh, Kin Wai Tang
-
Patent number: 11258023Abstract: A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.Type: GrantFiled: August 5, 2020Date of Patent: February 22, 2022Assignee: Nantero, Inc.Inventors: Mark Ramsbey, Thomas Rueckes, Tatsuya Yamaguchi, Syuji Nozawa, Nagisa Sato
-
Patent number: 11223013Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.Type: GrantFiled: February 28, 2017Date of Patent: January 11, 2022Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Qi Liu, Xiaolong Zhao, Sen Liu, Ming Liu, Hangbing Lv, Shibing Long, Yan Wang, Facai Wu
-
Patent number: 11211427Abstract: A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.Type: GrantFiled: April 17, 2019Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwoo Lee, Zhe Wu, Kyubong Jung, Seung-geun Yu, Ja Bin Lee
-
Patent number: 11205117Abstract: Neuromorphic devices are described. A neuromorphic device may include a pre-synaptic neuron; row lines extending from the pre-synaptic neuron in a first direction; a post-synapse neuron; a column line extending from the post-synaptic neuron in a second direction perpendicular to the first direction; and synapses disposed in intersection regions between the row lines and the column line. The synapses may include a first synapse having a first memristor; and a second synapse having a first selection device and a second memristor.Type: GrantFiled: March 6, 2018Date of Patent: December 21, 2021Assignee: SK HYNIX INC.Inventor: Seong-Hyun Kim
-
Patent number: 11201193Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.Type: GrantFiled: January 24, 2020Date of Patent: December 14, 2021Assignee: QUALCOMM IncorporatedInventors: Bin Yang, Xia Li, Gengming Tao
-
Patent number: 11193836Abstract: The invention relates to a strain gage and methods for making and using the same to measure strain of a surface of interest. In particular, the invention relates to a semiconductor strain gage held by a metal body using a ceramic interface between the gage and the body, which that can be attached to a surface of interest. The invention also relates to methods for making the ceramic interface and attaching the semiconductor strain gage to a surface of interest. The invention, including its various embodiments, also relates to using the semiconductor strain gage to measure strain at temperatures above 1000° F.Type: GrantFiled: January 30, 2019Date of Patent: December 7, 2021Inventors: Stanley Timothy Rosinski, Christopher Adam Suprock, Joseph James Christian
-
Patent number: 11127896Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.Type: GrantFiled: January 18, 2019Date of Patent: September 21, 2021Assignee: Everspin Technologies, Inc.Inventors: Syed M. Alam, Thomas Andre, Frederick Mancoff, Sumio Ikegawa
-
Patent number: 11127793Abstract: A manufacturing method of a three-dimensional vertical memory (3D-MV) includes the steps of: (A) forming a stack of interleaved lightly-doped layers and insulating layers; and, (B) a first photolithography step and an ion-implant step to form first and second regions in each lightly-doped layer. The first region, disposed around and shared by a plurality of memory holes, has a higher resistivity than the second region.Type: GrantFiled: January 24, 2021Date of Patent: September 21, 2021Assignees: HangZhou HaiCun Information Technology Co., Ltd.Inventor: Guobiao Zhang
-
Patent number: 11050018Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.Type: GrantFiled: October 26, 2019Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai, Chung-Ju Lee
-
Patent number: 11038108Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.Type: GrantFiled: May 24, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
-
Patent number: 11011227Abstract: Methods, systems and devices for operation of non-volatile memory device are described herein. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the non-volatile memory element.Type: GrantFiled: June 15, 2018Date of Patent: May 18, 2021Assignee: ARM Ltd.Inventors: Supreet Jeloka, Shidhartha Das, Mudit Bhargava, Saurabh Pijuskumar Sinha, James Edwards Myers
-
Patent number: 10985316Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.Type: GrantFiled: March 20, 2019Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yang Chen, Chun-Yang Tsai, Kuo-Ching Huang, Wen-Ting Chu, Pili Huang, Cheng-Jun Wu
-
Patent number: 10903422Abstract: A method for fabricating a semiconductor device including a vertically oriented memory structure includes forming at least one pillar including phase-change memory (PCM) material on at least one electrode, forming a plurality of spacers on the electrode and along sidewalls of the pillar, and forming, by processing the plurality of spacers and the pillar, a modified pillar having a vertically oriented dumbbell shape associated with a vertically oriented PCM memory structure.Type: GrantFiled: April 11, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Effendi Leobandung