Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.

Abstract: Provided is a phase change memory, including: at least one wiring layer each including a first conductive layer and a phase change layer horizontally disposed on the first conductive layer; a heater layer disposed to vertically contact with the at least one wiring layer; and a second conductive layer disposed to contact with the heater layer in parallel therewith, and through which current flows from at least one electrode into the at least one wiring layer. The phase change layer may be made of a phase change material and may have a thickness less than a thickness of the first conductive layer.

Abstract: A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability.

Abstract: A semiconductor device includes a first conductive layer; a second conductive layer; and a resistance variable element interposed between the first conductive layer and the second conductive layer and includes a doped first metal oxide layer and a second metal oxide layer. A density of oxygen vacancies of the second metal oxide layer is higher than that of the doped first metal oxide layer. The doped first metal oxide layer includes a doping material implanted thereto to suppress grains in the doped first metal oxide layer from increasing in size.

Abstract: A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element.

Abstract: A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. Other phase change memory cells are described. A method of forming a phase change memory cell and a phase change memory device are also described.

Abstract: A semiconductor device includes a conductive line, a diode on the conductive line, one or more insulating patterns adjacent to diode, and a data storage region coupled to the diode. An upper surface of the diode is between the one or more insulating patterns and the data storage region. The data storage region may include a phase-change region, and the diode may taper in width between two insulating patterns in one arrangement.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract: A nanoscale switching device comprises a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region containing a switching material; an area within the active region that constrains current flow between the first electrode and the second electrode to a central portion of the active region; and an interlayer dielectric layer formed of a dielectric material and disposed between the first and second electrodes outside the active region. A nanoscale crossbar array and method of forming the nanoscale switching device are also disclosed.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.

Abstract: A new class of phase change materials has been discovered based on compounds of: Ga; lanthanide; and chalcogenide. This includes compounds of Ga, La, and S (GLS) as well as related compounds in which there is substitution of S with O, Se and/or Te. Moreover, La can be substituted with other lanthanide series elements. It has been demonstrated that this class of materials exhibit low energy switching. For example, the GLS material can provide an optical recording medium with erasability 3-5 dB greater than the erasability of GeSbTe (GST) material which is the standard material for phase change memories.

Abstract: A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

Abstract: Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used in the ovonic threshold switch. The columnar morphology may cause cracks to occur which allow etchants used to etch the ovonic threshold switch to sneak through the ovonic threshold switch and to attack chalcogenides, either in the switch or in the memory element. In one embodiment, the electrode may be split into two metal nitride layers separated by an intervening metal layer.

Abstract: An electrical device includes a current transport layer formed using a layer of a topological material selected from the group of a topological insulator, a quantum anomalous hall (QAH) insulator, a topological insulator variant, and a topological magnetic insulator. In one embodiment, the current transport layer forms a conductive wire on an integrated circuit where the conductive wire includes two spatially separated edge channels, each edge channel carrying charge carriers propagating in one direction only. In other embodiments, an optical device includes an optical layer formed using a layer of the topological material. The optical layer can be a light absorbing layer, a light emitting layer, a light transport layer, or a light modulation layer.

Abstract: A nanoscale switching device is provided. The device comprises: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having a non-conducting portion comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field and a source portion that acts as a source or sink for the dopants; and an oxide layer either formed on the first electrode, between the first electrode and the active region or formed on the second electrode, between the second electrode and the active region. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided.

Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.

Abstract: Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.

Abstract: A sensor element is described that includes at least one semiconductor component having a gas-sensitive layer which is attached to a substrate by the flip-chip method, the gas-sensitive layer facing the substrate and a supply arrangement being provided to supply a gas to be examined to the gas-sensitive layer. The semiconductor component is enclosed in a casing. Also described is a method for manufacturing the sensor element, in which a semiconductor component having a gas-sensitive layer is attached by the flip-chip method to a substrate in such a way that the gas-sensitive layer faces the substrate. After that, the casing is applied by a plasma sputtering method, in particular an atmospheric plasma sputtering method. Finally, a use of the sensor element in the exhaust system of an internal combustion engine is also described.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.

Abstract: A semiconductor device includes a first semiconductor layer extending in a first direction on a substrate, a plurality of second semiconductor layers spaced apart in the first direction on the first semiconductor layer, and an insulation layer structure surrounding side walls of the first semiconductor layer and the plurality of second semiconductor layers. The first semiconductor layer may have a first conductivity type, and the plurality of second semiconductor layers may have a second conductivity type.

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

Abstract: A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element.

Abstract: Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material.

Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive unit, a second conductive unit, and a memory layer. The memory layer is provided between the first conductive unit and the second conductive unit. The memory layer is capable of reversibly transitioning between a first state with a low resistance and a second state with a higher resistance than the first state due to a current supplied via the first conductive unit and the second conductive unit. The memory layer has a chalcopyrite structure.

Abstract: An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active material is in electrical communication with the second electrode through the resistive layer.

Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.

Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: According to one embodiment, a storage device includes first electrodes, second electrodes, a resistance change layer provided between the first electrodes and the second electrodes, and ion metal particles that are formed in an island form between the first electrodes and the resistance change layer and that contain a metal movable inside the resistance change layer. The first electrodes and the second electrodes are formed of a material which is more unlikely to be ionized as compared to the metal, and the first electrodes are in contact with the resistance change layer in an area around the ion metal particles.

Abstract: A method of forming a semiconductor device structure. The method comprises forming a block copolymer assembly comprising at least two different domains over an electrode. At least one metal precursor is selectively coupled to the block copolymer assembly to form a metal-complexed block copolymer assembly comprising at least one metal-complexed domain and at least one non-metal-complexed domain. The metal-complexed block copolymer assembly is annealed in to form at least one metal structure. Other methods of forming a semiconductor device structures are described. Semiconductor device structures are also described.

Abstract: A phase change memory cell, an array of the phase change memory cells, and a method for fabricating the phase change memory cells. The phase change memory cell includes a bottom electrode, a heating element, and a heat shield. During programming of the phase change memory cell, the bottom electrode passes current to the phase change memory cell. The heating element is electrically coupled to the bottom electrode and generates heat during the programming of the phase change memory cell. The heat shield is thermally conductive and surrounds at least a portion of the heating element. The heat shield conducts heat generated during programming of the phase change memory cell to the bottom electrode.

Abstract: A molecular memory device has an insulating film with a cavity, the cavity having an upper portion and a lower portion; a first conductive member with a portion exposed at the lower portion of the cavity; a second conductive member with a portion exposed at the upper portion of the cavity; and a resistance varying-type molecular chain disposed in the cavity and bonded with the first conductive member or the second conductive member. The cavity is wider than at least one of the first conductive member along a first direction and the second conductive member along a second direction.

Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.

Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a titanium oxide-silicon-titanium oxide multilayer stack. Electrode materials may include one of ruthenium, titanium nitride, or carbon. The control element can include a silicon nitride-silicon-silicon nitride multilayer stack. Electrode materials may include titanium nitride.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.

Abstract: A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

Abstract: A memory device can include a plurality of memory elements formed over a substrate, including a plurality of first electrodes, each having a top surface and opposing side surfaces, a plurality of second electrodes formed on different vertical levels, each aligned with a corresponding first electrode in a lateral direction, and a memory material formed between each first electrode and an adjacent second electrode, the memory material being in contact with the opposing side surfaces of each first electrode and not in contact with the top surface of the first electrodes; wherein the memory material is electrically programmable between at least two different resistance states, and the lateral direction is parallel to a top surface of the substrate.