In Bipolar Transistor Structure Patents (Class 257/47)
  • Patent number: 10056518
    Abstract: An active photonic device having a Darlington configuration is disclosed. The active photonic device includes a substrate with a collector layer over the substrate. The collector layer includes an inner collector region and an outer collector region that substantially surrounds the inner collector region. A base layer resides over the collector layer. The base layer includes an inner base region and an outer base region that substantially surrounds and is spaced apart from the inner base region. An emitter layer resides over the base layer. The emitter layer includes an inner emitter region that is ring-shaped and resides over and extends substantially around an outer periphery of the inner base region. The emitter layer further includes an outer emitter region that is ring-shaped and resides over and extends substantially around the outer base region. A connector structure electrically couples the inner emitter region with the outer base region.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 21, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Kevin Wesley Kobayashi, Ricke Waylan Clark
  • Patent number: 9741671
    Abstract: A semiconductor die with backside protection includes an active region and a first polysilicon layer formed on a front side of a semiconductor substrate. A signal net is connected to the first polysilicon layer by way of a metal contact and a conductive wire is formed above the active region. During an invasive attack, when a trench is formed in the substrate and an electrically conductive filling is deposited in the trench, the signal net, the conductive wire, and the first polysilicon shape form a short-circuit, which renders the die dysfunctional and thereby foiling the invasive attack.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 22, 2017
    Assignee: NXP B.V.
    Inventors: Sven Trester, Claus Grzyb
  • Patent number: 9224701
    Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: December 29, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Sylvie Wuidart, Alexandre Sarafianos
  • Patent number: 9219113
    Abstract: A semiconductor device includes a substrate of a first conductivity type, a first impurity region of a second conductivity type formed on a top surface side of the substrate, a second impurity region of the second conductivity type formed on the top surface side of the substrate and in contact with the first impurity region, the second impurity region laterally surrounding the first impurity region and having a greater depth than the first impurity region, as viewed in cross-section, and a breakdown voltage enhancing structure of the second conductivity type formed to laterally surround the second impurity region. A boundary between the first and second impurity regions has a maximum impurity concentration equal to or less than that of the second impurity region, and a current is applied between a top surface and a bottom surface of the substrate.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: December 22, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Takahashi, Atsushi Narazaki, Tetsuo Takahashi
  • Patent number: 9076810
    Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alvin J. Joseph, Ramana M. Malladi, James A. Slinkman
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8921846
    Abstract: The present invention aims at providing an organic EL device that emits light by an alternating current, has a simple structure and provides little increase of production processes, while downsizing an overall configuration and a simplifying a method for producing said organic EL device. The organic EL device includes a power feeding part and an organic-EL-element forming part. The organic-EL-element forming part includes a plurality of unit EL elements formed on a substrate. There is provided a plurality of series-connected parts each formed by a plurality of the unit EL elements that are electrically connected in series in a forward direction. A plurality of the series-connected parts are electrically connected to the power feeding part in parallel. The series-connected parts that are connected in parallel include a series-connected part that is connected to the power feeding part so as to have a reverse polarity.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: December 30, 2014
    Assignee: Kaneka Corporation
    Inventors: Akira Nishikawa, Shigeru Ayukawa, Hideo Yamagishi
  • Patent number: 8895980
    Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: November 25, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhan Zhan, Qianqian Huang, Yangyuan Wang
  • Patent number: 8889439
    Abstract: The present disclosure involves a method of packaging light-emitting diodes (LEDs). According to the method, a plurality of LEDs is provided over an adhesive tape. The adhesive tape is disposed on a substrate. In some embodiments, the substrate may be a glass substrate, a silicon substrate, a ceramic substrate, and a gallium nitride substrate. A phosphor layer is coated over the plurality of LEDs. The phosphor layer is then cured. The tape and the substrate are removed after the curing of the phosphor layer. A replacement tape is then attached to the plurality of LEDs. A dicing process is then performed to the plurality of LEDs after the substrate has been removed. The removed substrate may then be reused for a future LED packaging process.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: November 18, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Min Lin
  • Patent number: 8872222
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8866194
    Abstract: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shinya Naito, Hideaki Fujiwara, Toru Dan
  • Patent number: 8809858
    Abstract: An integrated circuit including: a semiconductor substrate of a first conductivity type having at least one well of a second conductivity type laterally delimited, on two opposite walls, by regions of the first conductivity type, defined at its surface; at least one region of the second conductivity type which extends in the semiconductor substrate under the well; and a system for detecting a variation of the substrate resistance between each association of two adjacent regions of the first conductivity type.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 19, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Thierry Soudé, Alexandre Sarafianos, Francesco La Rosa
  • Patent number: 8809911
    Abstract: Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 8772885
    Abstract: The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: PixArt Imaging Incorporation, R.O.C.
    Inventors: Chuan-Wei Wang, Ming-Han Tsai
  • Patent number: 8692244
    Abstract: A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoto Kaguchi, Norihisa Asano, Katsumi Sato
  • Patent number: 8647537
    Abstract: An oxide sintered body includes indium oxide and gallium solid-solved therein, the oxide sintered body having an atomic ratio “Ga/(Ga+In)” of 0.001 to 0.12, containing indium and gallium in an amount of 80 atom % or more based on total metal atoms, and having an In2O3 bixbyite structure.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: February 11, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Futoshi Utsuno, Kazuyoshi Inoue, Hirokazu Kawashima, Masashi Kasami, Koki Yano, Kota Terai
  • Patent number: 8648391
    Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 8634236
    Abstract: Provided are a phase change memory device and a fabricating method thereof. The phase change memory device includes a substrate, an interlayer dielectric layer formed on the substrate, first and second contact holes formed in the interlayer dielectric layer, and a memory cell formed in the first and second contact holes and including a diode, a first electrode on the diode, a phase change material layer on the first electrode, and a second electrode on the phase change material layer, wherein the first contact hole and the second contact hole are spaced apart from and separated from each other.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Young Park, Jeong-Hee Park, Hyun-Suk Kwon
  • Patent number: 8634442
    Abstract: An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about ?1 degree towards (000-1) and less than about +/?0.3 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. In a preferred embodiment, the laser stripe region is characterized by a cavity orientation that is substantially parallel to the c-direction, the laser stripe region having a first end and a second end. The device includes a first cleaved c-face facet, which is coated, provided on the first end of the laser stripe region. The device also has a second cleaved c-face facet, which is exposed, provided on the second end of the laser stripe region.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: January 21, 2014
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Daniel F. Feezell, Nicholas J. Pfister, Rajat Sharma, Mathew C. Schmidt, Christiane Poblenz, Yu-Chia Chang
  • Patent number: 8604590
    Abstract: A bipolar transistor structure with multiple electrodes configured to include an enhanced base capacitive element. Alternatively, a transistor with an integrated light emitting capacitive (LEC) element at the source or drain of the transistor. The transistor may be a stand alone transistor for usage in discrete applications, or may be implemented in a pixel circuit used in a display apparatus. In the pixel circuit embodiment, driver circuitry causes appropriate charging and discharging of the LEC elements of respective pixels to provide a desired display. In one alternative, a transistor may be configured to have multiple LEC elements integrated therewith, to provide respective different colors used in forming a display.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: December 10, 2013
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Leonard D. Nicoletti
  • Patent number: 8519491
    Abstract: The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: August 27, 2013
    Assignee: Pixart Imaging Incorporation, R.O.C.
    Inventors: Chuan-Wei Wang, Ming-Han Tsai
  • Patent number: 8455975
    Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 4, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wensheng Qian
  • Patent number: 8422525
    Abstract: An optical device capable of emitting light having a wavelength ranging from about 490 to about 580 nanometers has a gallium nitride substrate with a semipolar crystalline surface region characterized by an orientation of greater than 3 degrees from (11-22) towards (0001) but less than about 50 degrees. A laser stripe formed on the substrate has a cavity orientation substantially parallel to the m-direction.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: April 16, 2013
    Assignee: Soraa, Inc.
    Inventors: James W. Raring, Daniel F. Feezell, Nicholas J. Pfister
  • Patent number: 8314032
    Abstract: A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tetsufumi Kawamura, Hiroyuki Uchiyama, Hironori Wakana, Mutsuko Hatano, Takeshi Sato
  • Patent number: 8300448
    Abstract: A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode (106) is formed to sandwich an insulating film (105) with a p-type semiconductor region (102). A first n-type semiconductor region (103) and a second n-type semiconductor region (104) are formed in the p-type semiconductor region (102) at two sides of the selection electrode (106). A first resistance-changing layer (107) is connected to the first n-type semiconductor region (103), and a second resistance-changing layer (109) is connected to the second n-type semiconductor region (104). In addition, a first wiring layer (108) is connected to the second resistance-changing layer (109), and a second wiring layer (110) is connected to the second resistance-changing layer (109).
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: October 30, 2012
    Assignee: NEC Corporation
    Inventor: Masayuki Terai
  • Patent number: 8227832
    Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 24, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Tzuyin Chiu, Zhengliang Zhou, Xiongbin Chen
  • Patent number: 8193563
    Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Peter Gambino, Steven Howard Voldman, Michael Joseph Zierak
  • Patent number: 7960753
    Abstract: A surface plasmon polaritron activated semiconductor device uses a surface plasmon wire that functions as an optical waveguide for fast communication of a signal and functions as a energy translator using a wire tip for translating the optical signal passing through the waveguide into plasmon-polaritron energy at a connection of the semiconductor device, such as a transistor, to activate the transistor for improved speed of communications and switching for preferred use in digital systems.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: June 14, 2011
    Assignee: The Aerospace Corporation
    Inventors: Joshua A. Conway, Ryan A. Stevenson, Jon V. Osborn
  • Patent number: 7943970
    Abstract: Provided is a method of detecting the presence of a target bio-molecule or a concentration of the bio-molecule using a field effect transistor. The method includes: contacting a first sample having a first target bio-molecule with a reference electrode of a field effect transistor; measuring a first electric signal change of the field effect transistor; contacting a second sample with a sensing surface of the same field effect transistor; measuring a second electric signal change of the field effect transistor; and comparing the first electric signal with the second electric signal.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-tae Yoo, Kyu-sang Lee, Jeo-young Shim, Won-seok Chung, Yeon-ja Cho
  • Patent number: 7868382
    Abstract: A power actuator of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of the bipolar transistor and a source terminal of the DMOS transistor and having respective control terminals. Advantageously, the power actuator further comprises at least a Zener diode, inserted between the source terminal of the DMOS transistor and the control transistor of the bipolar transistor.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: January 11, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cesare Ronsisvalle, Vincenzo Enea
  • Patent number: 7863610
    Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: January 4, 2011
    Assignees: Qimonda North America Corp., International Business Machines Corporation
    Inventors: Bipin Rajendran, Shoaib Hasan.Zaidi
  • Patent number: 7795614
    Abstract: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a phase-separated dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the semiconductor layer.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: September 14, 2010
    Assignee: Xerox Corporation
    Inventors: Yiliang Wu, Hadi K Mahabadi, Beng S Ong, Paul F Smith
  • Patent number: 7704824
    Abstract: The present invention provides a highly doped semiconductor layer. More specifically, the present invention provides a semiconductor layer that includes at least two impurities. Each impurity is introduced at a level below its respective degradation concentration. In this manner, the two or more impurities provide an additive conductivity to the semiconductor layer at a level above the conductivity possible with any one of the impurities alone, due to the detrimental effects that would be created by increasing the concentration of any one impurity beyond its degradation concentration.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: April 27, 2010
    Assignee: RF Micro Devices, Inc.
    Inventors: Matthew L. Seaford, Arthur E. Geiss, Wayne Lewis, Larry W. Kapitan, Thomas J. Rogers
  • Patent number: 7635879
    Abstract: This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of an antimony-based material deposited on the collector layer, an emitter layer of an antimony-based material deposited on the base layer, and a cap layer of an antimony-based material deposited on the emitter layer.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: December 22, 2009
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: John Bradley Boos, Brian R. Bennett, Paul Campbell, Richard Magno
  • Patent number: 7598521
    Abstract: A semiconductor device includes a semiconductor chip having a collector region, a base region, and an emitter region that are formed in a semiconductor substrate. The semiconductor chip also includes a base electrode strip in contact with the base region, an emitter electrode strip in contact with the emitter region, an emitter electrode plate disposed above the base electrode strip and the emitter electrode strip, and a base electrode plate disposed adjacent the emitter electrode plate. The device also includes a base terminal external to the semiconductor chip and connected to the base electrode plate and an emitter terminal external to the semiconductor chip and connected to the emitter electrode plate. The base terminal and the emitter terminal are disposed along an edge of the semiconductor chip, and the base electrode strip and the emitter electrode strip are perpendicular to the edge of the semiconductor chip.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: October 6, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Osamu Akaki
  • Patent number: 7582494
    Abstract: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: September 1, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shine Chien Chung, David Lu
  • Patent number: 7482642
    Abstract: A bipolar transistor which has a base formed of a combination of shallow and deep acceptors species. Specifically, elements such as Indium, Tellurium, and Gallium are deep acceptors in silicon, and are appropriate for such an application, in combination with boron as the shallow acceptor. The use of a deep acceptor for doping the base of the transistor has the benefit of providing a doping species, which increases in ionization as the temperature rises. At elevated temperatures, the fraction of, for example, indium which is ionized increases and it results in an increased Gummel number, driving down the current gain. In other words, the enhancement of the Gummel number between room temperature and an elevated temperature compensates for the increase in the ratio of collector and base currents due to band gap narrowing effects. Thus, a zero temperature coefficient bipolar transistor is provided.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: January 27, 2009
    Assignee: LSI Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 7473983
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: January 6, 2009
    Assignee: Intersil Americas Inc.
    Inventor: James Douglas Beasom
  • Publication number: 20080288662
    Abstract: An identification address of a sensor interface device is configured in response to the order of connection of first (DXP1) and second (DXN1) package pins to electrodes of a sensor (Q0). A sensor signal processing circuit (23) has first and second inputs coupled through the first and second pins to the sensor for converting a parameter sensed by the sensor to a different representation. A current is forced through the first pin to produce either a high or low voltage on the first pin depending on the order of connection of the first and second pins to the electrodes of the sensor. A voltage on the first pin is compared with a reference voltage to produce a comparison signal which is mapped to produce the identification address.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventor: Jerry L. Doorenbos
  • Patent number: 7304334
    Abstract: Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: December 4, 2007
    Assignee: Cree, Inc.
    Inventors: Anant K. Agarwal, Sumithra Krishnaswami, Sei-Hyung Ryu, Edward Harold Hurt
  • Patent number: 7271078
    Abstract: A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×1012˜1.5×1013atoms/cm2 performed at an energy level of 10˜100keV.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 18, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Wan Bang
  • Patent number: 7173274
    Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: February 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Douglas Duane Coolbaugh, James Stuart Dunn, David R. Greenberg, David L. Harame, Basanth Jagannathan, Robb Allen Johnson, Louis D. Lanzerotti, Kathryn Turner Schonenberg, Ryan Wayne Wuthrich
  • Patent number: 7008852
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6958491
    Abstract: Test probe pads are located lateral to, and spaced from, the emitter, base or collector region of a bipolar transistor, preferably on separate pedestals, and connected to their respective transistor regions by air bridges. The probe pads, transistor contacts and air bridges are preferably formed as common metallizations. In the case of an HBT, a gap in the subcollector below the air bridges insulates the test transistor from capacitor loading by the probe pads. The test transistors can be used to characterize both themselves and functional circuit transistors fabricated with the same process on the same wafer by testing at an intermediate stage of manufacture, thus allowing wafers to be discarded without completing the manufacture if their transistors do not meet specifications.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: October 25, 2005
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: Berinder P. S. Brar, James Chingwei Li, John A. Higgins
  • Patent number: 6949764
    Abstract: A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: September 27, 2005
    Assignee: International Business Machines Corporation
    Inventor: Tak Hung Ning
  • Patent number: 6939771
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6917061
    Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 12, 2005
    Assignee: Microlink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Patent number: 6870184
    Abstract: A bipolar junction transistor (BJT) requires the fabrication of a BJT structure and of a support post which is adjacent to, but physically and electrically isolated from, the BJT structure. The BJT structure includes a semi-insulating substrate, a subcollector, a collector, a base, and an emitter. Metal contacts are formed on the subcollector and emitter to provide collector and emitter terminals. Contact to the structure's base is accomplished with a metal contact which extends from the top of the support post to the edge of the base nearest the support post. The contact bridges the physical and electrical separation between the support post and the base and provides a base terminal for the device. The base contact need extend over the edge of the base by no more than the transfer length associated with the fabrication process. This results in the smaller base contact area over the collector than would otherwise be necessary, and a consequent reduction in base-collector capacitance.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Innovative Technology Licensing, LLC
    Inventors: James Chingwei Li, Richard L. Pierson, Jr., Berinder P. S. Brar, John A. Higgins
  • Patent number: RE43042
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: December 27, 2011
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: RE44140
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: April 9, 2013
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom