In Bipolar Transistor Structure Patents (Class 257/47)
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Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS
Patent number: 6849871Abstract: A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.Type: GrantFiled: January 10, 2001Date of Patent: February 1, 2005Assignee: International Business Machines CorporationInventor: Tak Hung Ning -
Patent number: 6831293Abstract: A p-n junction-type compound semiconductor light-emitting device having a substrate formed of a single crystal, a first barrier layer provided on the substrate and formed of a compound semiconductor of a first conduction type, a light-emitting layer provided on the first barrier layer and formed of an indium (In)-containing group III nitride semiconductor of a first or a second conduction type, and an evaporation-preventing layer provided on the light-emitting layer for preventing the evaporation of indium from the light-emitting layer. The evaporation-preventing layer is formed of an undoped boron phosphide (BP)-base semiconductor of a second conduction type. A method for producing the semiconductor-light emitting device is also disclosed.Type: GrantFiled: March 18, 2003Date of Patent: December 14, 2004Assignee: Showa Denko Kabushiki KaishaInventor: Takashi Udagawa
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Patent number: 6809400Abstract: This disclosure describes a structure for transistor devices formed from compound semiconductor materials; and particularly for heterojuntion bipolar transistors (HBTs); and more particularly for the collector structure of a double HBT (DHBT). The invention enables high output power at high frequency operation, of high frequency operation at high output power.Type: GrantFiled: March 14, 2003Date of Patent: October 26, 2004Inventors: Eric Harmon, Jerry Woodall, Hironori Tsukamoto, David Salzman
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Patent number: 6774411Abstract: According to a disclosed embodiment, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequently, an opening is fabricated in the dielectric layer, and an emitter layer is formed on top of the dielectric layer and in the opening. Thereafter, an anisotropic polymerizing etch chemistry is utilized to etch the emitter layer down to a first depth, forming an emitter region in the opening. Next, a non-polymerizing etch chemistry having isotropic components is used to create a notch in the dielectric layer below the emitter region. The formation of the notch reduces the overlap area of a capacitor that forms between the emitter region and the base region, which translates to a lower level of emitter to base capacitance.Type: GrantFiled: July 10, 2002Date of Patent: August 10, 2004Assignee: Newport Fab, LLCInventor: Klaus F. Schuegraf
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Patent number: 6727516Abstract: A power conversion apparatus has a circuit configuration in which a collector voltage of an IGBT is divided. It also has a unit which protects the IGBT against overvoltages applied to the collector by outputting a potential of a voltage dividing point to a gate of the IGBT. A case of a resistor on the high-voltage side of the voltage dividing point is fixed to an emitter potential of the IGBT.Type: GrantFiled: March 12, 2002Date of Patent: April 27, 2004Assignee: Hitachi, Ltd.Inventors: Shuji Katoh, Shigeta Ueda, Hiromitsu Sakai, Takashi Ikimi, Tomomichi Ito
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Publication number: 20040065878Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.Type: ApplicationFiled: April 15, 2003Publication date: April 8, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh, Paul A. Clifton
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Patent number: 6717177Abstract: A power conversion apparatus has a circuit configuration in which a collector voltage of an IGBT is divided. It also has a unit which protects the IGBT against overvoltages applied to the collector by outputting a potential of a voltage dividing point to a gate of the IGBT. A case of a resistor on the high-voltage side of the voltage dividing point is fixed to an emitter potential of the IGBT.Type: GrantFiled: March 28, 2003Date of Patent: April 6, 2004Assignee: Hitachi, Ltd.Inventors: Shuji Katoh, Shigeta Ueda, Hiromitsu Sakai, Takashi Ikimi, Tomomichi Ito
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Patent number: 6677621Abstract: There is provided a light emitting device which is bright and has low electric power consumption and high reliability. A triplet EL element 203 electrically connected to a current controlling TFT 102 is provided in a pixel portion 201. A luminescent material used for the triplet EL element 203 has a feature that EL is obtained by triplet excitation, and exhibits high luminous efficiency at a low operation voltage as compared with the prior art. Accordingly, the operation is made at the low operation voltage, so that the light emitting device which is bright and has low electric power consumption and high reliability can be obtained.Type: GrantFiled: May 21, 2001Date of Patent: January 13, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kazutaka Inukai
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Publication number: 20030237061Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.Type: ApplicationFiled: June 19, 2002Publication date: December 25, 2003Applicant: FormFactor, Inc.Inventors: Charles A. Miller, Timothy Cooper, Yoshikazu Hatsukano
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Publication number: 20030127645Abstract: A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.Type: ApplicationFiled: December 10, 2002Publication date: July 10, 2003Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Miron Drobnis, Martin J. Hill
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Patent number: 6569730Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: March 6, 2002Date of Patent: May 27, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6545340Abstract: A semiconductor device of the invention in the form of a superlattice-heterojunction bipolar transistor (SL-HBT) 10 incorporates a superlattice region 16 within an emitter mesa 21. The superlattice region 16 provides a non-linear response to a sufficiently high level of device current to counteract thermal runaway. This protects the device from damaging levels of current. The device 10 may be a radio-frequency SL-HBT with performance equivalent to that of a conventional heterojunction bipolar transistor. The invention may also be implemented as a semiconductor laser.Type: GrantFiled: March 6, 2001Date of Patent: April 8, 2003Assignee: Qinetiq LimitedInventors: Anthony W Higgs, David G Hayes, Robert G Davis
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Patent number: 6465804Abstract: A heterojunction bipolar transistor (HBT) having an emitter structure capable of reducing the current crowding effect and preventing thermal instabilities is disclosed, wherein a negative differential resistance. (NDR) element is added to the layer structure of the conventional emitter. In accordance with the invention, the NDR element can be implemented, for example, by a Resonant Tunnel Diode (RTD) or an Esaki Diode structure. The NDR element is designed to limit the tunneling current to the maximal emitter current density required for safe transistor operation, thereby also reducing the current crowding effect.Type: GrantFiled: July 10, 2000Date of Patent: October 15, 2002Assignee: Technion Research & Development Foundation Ltd.Inventors: Nachum Shamir, Dan Ritter
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Patent number: 6465870Abstract: A ESD (electrostatic discharge) robust SiGe bipolar transistor is provided which comprises a substrate of a first conductivity type; a doped subcollector region of a second conductivity type formed on the substrate, the doped subcollector region including an epitaxial collector region which is defined between isolation trench regions; a first film comprising silicon and germanium formed on the doped subcollector region, the first film including a single crystal SiGe intrinsic base region and an extrinsic SiGe polysilicon base regions of the first conductivity type abutting the intrinsic base region; a second film comprising an emitter of the second conductivity type contained over the intrinsic base region formed by an emitter window mask and a second region formed outside of the emitter; a first doped region of the first conductivity type formed at a facet point between the intrinsic base region and one of the extrinsic base regions; a second doped region of said first conductivity type contained at the outeType: GrantFiled: January 25, 2001Date of Patent: October 15, 2002Assignee: International Business Machines CorporationInventor: Steven Howard Voldman
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Publication number: 20020117665Abstract: The present invention relates to a hetero-bipolar transistor. This transistor comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer on the buffer layer, a collector layer on the sub-collector layer, a base layer on the collector layer, a wide-gap emitter layer on the base layer and a emitter contact layer on the emitter layer. The emitter layer extends the emitter contact layer, so the edge of the emitter layer is apart from the emitter contact layer and entirely covers the region where the collector layer and the sub-collector layer are overlapped to each other. According to this configuration, the transistor shows the enhanced reliability and the improved high frequency performance.Type: ApplicationFiled: February 26, 2002Publication date: August 29, 2002Inventors: Seiji Yaegassi, Kenji Kotani, Masaki Yanagisawa, Hiroshi Yano
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Patent number: 6396125Abstract: A semiconductor device is formed of a casing, a semiconductor element disposed in the casing, and a control terminal assembly situated outside the casing. The control terminal assembly includes control terminals connected to the semiconductor element, and slit-shape openings at at least two sides adjacent to each other for receiving therein projecting terminals of a connector. Since the terminals of the control terminal assembly are contained in a housing, deformation of the terminals due to external force is avoided, and mis-engagement in connection with the projecting terminal does not occur, and electrostatic break down of an element in the power module during handling is also prevented.Type: GrantFiled: July 24, 2000Date of Patent: May 28, 2002Assignee: Fuji Electric Co., Ltd.Inventor: Shin Soyano
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Patent number: 6274921Abstract: A semiconductor integrated circuit has a protective NMOS transistor having a drain and a source respectively electrically connected to a first interconnection (electrically connected to a base electrode of a bipolar transistor or a gate electrode of a MOS transistor) and ground and a gate electrode in a floating state, upon formation of the first interconnection. The first interconnection is formed by patterning using plasma etching and is connected to ground after the formation of the first interconnection.Type: GrantFiled: April 17, 1998Date of Patent: August 14, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kouichi Hasegawa
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Patent number: 6208012Abstract: The invention provides a zener zap diode having a high reliability and a method of manufacturing the same that can remove the problems accompanied with the zener zap trimming. In order to attain the object, the zener zap diode according to the invention is constructed such that, in an area adjacent to the surface of a semiconductor substrate, an active base region, an outer base region, and an emitter region are formed. Furthermore, a base lead electrode (one polysilicon layer) is formed to overlay the outer base region, and an emitter lead electrode (another polysilicon layer) is formed above the active base region. A contact between the one polysilicon layer and a metal interconnecting layer is disposed right above the outer base region. Since the insulation film that hinders the filament from being formed is not disposed under the one polysilicon layer, a filament is widely formed into an N-type well region when a PN junction is zapped by the zener zap trimming method.Type: GrantFiled: January 22, 1997Date of Patent: March 27, 2001Assignee: Sony CorporationInventor: Tetsuya Oishi
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Patent number: 5872369Abstract: A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.Type: GrantFiled: January 30, 1997Date of Patent: February 16, 1999Assignee: Oki Electric Industry Co., Ltd.Inventor: Kazuyuki Inokuchi
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Patent number: 5744822Abstract: Amorphous silicon in impurity regions (source and drain regions or N-type or p-type regions) of TFT and TFD are crystallized and activated to lower electric resistance, by depositing film having a catalyst element such as nickel (Ni), iron (Fe), cobalt (Co) or platinum (Pt) on or beneath an amorphous silicon film, or introducing such a catalyst element into the amorphous silicon film by ion implantation and subsequently crystallizing the same by applying heat annealing at an appropriate temperature.Type: GrantFiled: January 24, 1997Date of Patent: April 28, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Yasuhiko Takemura
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Patent number: 5369304Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.Type: GrantFiled: August 14, 1992Date of Patent: November 29, 1994Assignee: Motorola, Inc.Inventors: Israel A. Lesk, Francine Y. Robb, Lewis E. Terry, Frank S. d'Aragona
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Patent number: 5254485Abstract: There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction type to be a collector through a non-single crystalline semiconductor thin film, a second semiconductor thin film is formed on the first semiconductor thin film, and an impurity of the first conduction type is introduced in the second semiconductor thin film after patterning the first and second semiconductor thin film so as to form an emitter electrode.Type: GrantFiled: September 17, 1991Date of Patent: October 19, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Shuichi Kameyama, Hiroshi Shimomura, Atsushi Hori
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Patent number: 5217909Abstract: A method for manufacturing a bipolar transistor in which the base, emitter and collector terminals are produced from a single, planar layer of, for example, polysilicon, directly deposited onto a substrate. The planar layer is doped by a first conductivity type for the base terminal. After masking with an implantation mask, covering a region of the planar layer for the base terminal and defining regions of the planar layer for the emitter and collector terminals, the regions for the emitter and collector terminals are doped by an implantation of a second conductivity type, the second conductivity type being opposite the first conductivity type. After a self-aligned supplementation of the implantation mask, for example, with the assistance of a spacer technique, with which the regions of the planar layer for the emitter and collector terminals are also covered, the planar layer is structured by anisotropic etching by using the supplemented implantation mask as an etching mask.Type: GrantFiled: June 10, 1991Date of Patent: June 8, 1993Assignee: Siemens AktiengesellschaftInventor: Emmerich Bertagnolli