With Doping Profile To Adjust Barrier Height Patents (Class 257/475)
  • Patent number: 11264450
    Abstract: The embodiments of the invention provides a semiconductor device and a method for manufacturing it The semiconductor device provided by the embodiments of the invention comprises: a first electrode layer; a substrate layer positioned on the first electrode layer; an epitaxy layer positioned on the substrate layer and comprising a first surface far from the substrate layer; a plurality of well regions disposed by extending from the first surface into the epitaxy layer and orthographic projections thereof on the first surface are spaced from each other; a second electrode layer, comprising first metal layers, each disposed between adjacent two of the well regions on the first surface and forms a Schottky contact with the epitaxy layer, wherein the Schottky contact has variable barrier height. The semiconductor device provided by the embodiments of the invention may improve the forward conduction ability without affecting the reverse blocking ability.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 1, 2022
    Assignee: WeEn Semiconductors Technology Co., Ltd.
    Inventors: Jingjing Cui, Eddie Huang, Jianfeng Zhang
  • Patent number: 11217707
    Abstract: A Schottky device includes a silicon carbide (SiC) substrate of a first conductivity type, a drift layer of the first conductivity type, a trench, a barrier layer of a second conductivity type, an electrically conductive material that at least partially fills the trench and contacts the barrier layer, a first electrode, and a second electrode. The drift layer is formed of SiC and is situated onto the SiC substrate. The trench extends from the top surface of the drift layer towards the SiC substrate. The barrier layer contacts the drifting layer and covers a sidewall and a bottom wall of the trench. The first electrode forms a Schottky junction with the drift layer and forms a low resistivity contact with the barrier layer and the electrically conductive material. The second electrode forms an ohmic contact with the SiC substrate.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 4, 2022
    Inventors: Wing Chong Tony Chau, Wing Kit Cheung, Wai Tien Chan
  • Patent number: 10840385
    Abstract: An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conduction type comprising a voltage blocking layer; and islands of a second conductivity type on a contact surface; and a metal layer on the voltage blocking layer, wherein the metal layer and the voltage blocking layer includes a Schottky contact, and a first conductivity type layer comprising the first conduction type not in contact with the Schottky contact that is interspersed between the islands of the second conductivity type.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 17, 2020
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 10700219
    Abstract: A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Jefferson W. Hall
  • Patent number: 10547252
    Abstract: A first drive circuit is connected with a first power supply node and a first GND node. A second drive circuit is connected with a second power supply node and a second GND node electrically separated from the first power supply node and the first GND node, respectively. A PN junction portion is formed of a P type part electrically connected with the first GND node, and an N type part electrically connected with the second power supply node. A magnetic coupling element has a first conductor coil and a second conductor coil. The first conductor coil is electrically connected with output nodes of the first drive circuit. The second conductor coil is electrically connected with input nodes of the second drive circuit.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Motoki Imanishi
  • Patent number: 10249550
    Abstract: The present invention provides a power module and a manufacturing method thereof. The power module includes a carrier board and a lead component stacked relative to the carrier board. The lead component includes an initial plane, plural first pins and plural second pin. The initial plane includes a vertical projection overlapping with the carrier board. The first pins are electrically connected to the carrier board and vertical to the initial plane. The second pins are electrically connected to the carrier board and vertical to the initial plane. An isolation gap is disposed in the initial plane and located between the first pins and the second pins. The initial plane is separated into a first plane and a second plane by the isolation gap, so as to electrically isolate the first pins and the second pins from each other.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 2, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Pengkai Ji, Shouyu Hong, Zhenqing Zhao, Jianhong Zeng
  • Patent number: 9640672
    Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: May 2, 2017
    Assignees: National Central University, Delta Electronics, Inc.
    Inventors: Jen-Inn Chyi, Bo-Shiang Wang, Chun-Chieh Yang, Geng-Yen Lee
  • Patent number: 9577044
    Abstract: A semiconductor device includes first and second second-conductivity-type region groups containing multiple second-conductivity-type regions that are disposed on a first silicon carbide semiconductor layer of a first conductivity type, arrayed in parallel following one direction with a space between each other, and first and second electrodes disposed on the first silicon carbide semiconductor layer and forming a Schottky junction with the first silicon carbide semiconductor layer. The first electrode covers a position where a distance from adjacent first and second second-conductivity-type regions included in a first second-conductivity-type region group, and a distance from a third second-conductivity-type region included in a second second-conductivity-type region group and adjacent to the first and second second-conductivity-type regions, are equal.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 21, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masao Uchida, Masashi Hayashi, Koutarou Tanaka
  • Patent number: 9537017
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: January 3, 2017
    Assignee: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
  • Patent number: 9525024
    Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Su, Huang-Ming Chen, Chun-Feng Nieh, Pei-Chao Su
  • Patent number: 9263597
    Abstract: A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n+ substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n+ substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 16, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 9230958
    Abstract: A silicon carbide epitaxial layer formed by a low concentration wide band gap semiconductor of a first conductivity type is formed on the surface of a silicon carbide substrate formed by a high concentration wide band gap semiconductor of the first conductivity type. A Schottky electrode is formed on the silicon carbide epitaxial layer. The interface between the Schottky electrode and the silicon carbide epitaxial layer is used as a Schottky interface. Plural impurity regions of a second conductivity type are disposed at predetermined intervals in a lateral direction, in the silicon carbide epitaxial layer, at a position in the lower portion of the Schottky electrode in the depth direction. Because of the shape of the impurity regions, any leak current can be suppressed without raising the ON-resistance.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 5, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Takashi Tsuji, Kenji Fukuda
  • Patent number: 9212055
    Abstract: Aligned nanowire arrays were coated with semiconductor shell layers, and optionally with noble metal nanoparticles for use as three dimensional gas sensors. The sensors show room-temperature responses to low concentrations of various gases. Arrays containing different sensor types can discriminate among different gases, based upon changes in conductivity and response times.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: December 15, 2015
    Inventors: Weilie Zhou, Jiajun Chen, Kai Wang
  • Patent number: 9082628
    Abstract: A trench Schottky diode is described, which has a highly doped substrate of a first conductivity type and an epitaxial layer of the same conductivity type that is applied to the substrate. At least two trenches are introduced into the epitaxial layer. The epitaxial layer is a stepped epitaxial layer that has two partial layers of different doping concentrations.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 14, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach
  • Publication number: 20150144966
    Abstract: A semiconductor component includes a semiconductor body of a first conduction type and a metal layer on the semiconductor body, wherein the metal layer forms with the semiconductor body a Schottky contact along a contact surface. A doping concentration of the first conduction type on the contact surface varies along a direction of the contact surface.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Inventors: Jens Peter Konrath, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 9006858
    Abstract: In a Schottky diode having an n+-type substrate, an n-type epitaxial layer, at least two p-doped trenches introduced into the n-type epitaxial layer, mesa regions between adjacent trenches, a metal layer functioning as a cathode electrode, and another metal layer functioning as an anode electrode, the thickness of the epitaxial layer is more than four times the depth of the trenches.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 14, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Publication number: 20150084153
    Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalk and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.
    Type: Application
    Filed: January 21, 2014
    Publication date: March 26, 2015
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mingjiao Liu, Michael Thomason
  • Patent number: 8975719
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
  • Publication number: 20150061067
    Abstract: A semiconductor device includes an epitaxial layer of a first conductive type; an anode electrode and a cathode electrode arranged on the epitaxial layer to be separated from each other; a first drift layer of the first conductive type formed in the epitaxial layer; a Schottky contact area at a region of contact between the anode electrode and the first drift layer; an impurity region of a second conductive type different from the first conductive type at the epitaxial layer; and an insular impurity region formed below the Schottky contact area.
    Type: Application
    Filed: July 22, 2014
    Publication date: March 5, 2015
    Inventors: Hyun-Ju Kim, Jae-June Jang, Hoon Chang, Jae-Ho Kim, Kyu-Heon Cho
  • Patent number: 8969995
    Abstract: High-efficiency Schottky diodes (HED) and rectifier systems having such semiconductor devices are provided, which Schottky diodes (HED) are composed of at least one Schottky diode combined with an additional semiconductor element, e.g., with magnetoresistors (TMBS) or with pn diodes (TJBS), and have trenches. Such high-efficiency Schottky diodes make it possible to construct rectifiers which are suitable for higher temperatures and can therefore be used in motor vehicle generators, without particular cooling measures such as heat sinks being required.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Gert Wolf, Markus Mueller
  • Patent number: 8969994
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli
  • Patent number: 8901699
    Abstract: Integral structures that block the current conduction of the built-in PiN diode in a junction barrier Schottky (JBS) structure are provided. A Schottky diode may be incorporated in series with the PiN diode, where the Schottky diode is of opposite direction to that of the PiN diode. A series resistance or and insulating layer may be provided between the PiN diode and a Schottky contact. Silicon carbide Schottky diodes and methods of fabricating silicon carbide Schottky diodes that include a silicon carbide junction barrier region disposed within a drift region of the diode are also provided. The junction barrier region includes a first region of silicon carbide having a first doping concentration in the drift region of the diode and a second region of silicon carbide in the drift region and disposed between the first region of silicon carbide and a Schottky contact of the Schottky diode. The second region is in contact with the first region of silicon carbide and the Schottky contact.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: December 2, 2014
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal
  • Patent number: 8896084
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: November 25, 2014
    Assignees: Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8878329
    Abstract: A high voltage device having a Schottky diode integrated with a MOS transistor includes a semiconductor substrate a Schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the Schottky diode, and a control gate covering a portion of the Schottky diode and the first doped region positioned on the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 4, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Min-Hsuan Tsai
  • Patent number: 8860169
    Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
  • Publication number: 20140252484
    Abstract: An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Gary H. Loechelt, Prasad Venkatraman, Zia Hossain, Gordon M. Grivna
  • Patent number: 8816467
    Abstract: A semiconductor device including a Schottky diode of the trench-junction-barrier type having an integrated PN diode, and a corresponding method for manufacturing the device, are provided. An n layer is provided on an nt substrate, and trenches are provided in the n layer. The trenches are provided with p-doped regions. The nt substrate and the n layer carry a contact layer.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: August 26, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Alfred Goerlach, Ning Qu
  • Patent number: 8816468
    Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 26, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
  • Publication number: 20140231867
    Abstract: A diode is provided with a pillar region formed so as to extend between a barrier region and an anode electrode, contact the barrier region, and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region; and a barrier height adjusting region formed so as to be located between the pillar region and the anode electrode, and contact the pillar region and the anode electrode. The barrier height adjusting region includes at least one component selected from the group consisting of a second conductivity type semiconductor having a concentration lower than that of an anode region, the first conductivity type semiconductor having a concentration lower than that of the pillar region, and an i-type semiconductor. The barrier height adjusting region and the anode electrode are connected through a Schottky junction.
    Type: Application
    Filed: January 15, 2014
    Publication date: August 21, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yusuke YAMASHITA, Satoru MACHIDA, Jun SAITO, Masaru SENOO, Jun OKAWARA
  • Patent number: 8809902
    Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 19, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
  • Patent number: 8796808
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 5, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Publication number: 20140203299
    Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.
    Type: Application
    Filed: July 27, 2012
    Publication date: July 24, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Yuta Yokotsuji
  • Publication number: 20140183434
    Abstract: Semiconductor devices, and methods of fabricating the same, include a metal-containing layer on a semiconductor layer, and a barrier-lowering portion between the metal-containing layer and the semiconductor layer. The barrier-lowering portion lowers a Schottky barrier height between the metal-containing layer and the semiconductor layer below a Schottky barrier height between a metal silicide layer and the semiconductor layer.
    Type: Application
    Filed: October 28, 2013
    Publication date: July 3, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hanjin LIM, Wonseok YOO, Insang JEON, Seokwoo NAM, Kongsoo LEE, Jaejong HAN
  • Publication number: 20140167072
    Abstract: A schottky barrier diode includes an n? type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n? type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n? type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n? type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n? type epitaxial layer.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 19, 2014
    Applicant: HYUNDAI MOTOR COMPANY
    Inventors: Dae Hwan CHUN, Jong Seok LEE, Kyoung-Kook HONG, Youngkyun JUNG
  • Publication number: 20140145289
    Abstract: The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 29, 2014
    Applicant: Cree, Inc.
    Inventor: Qingchun Zhang
  • Publication number: 20140061847
    Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
  • Publication number: 20140035090
    Abstract: A trench Schottky diode is described, which has a highly doped substrate of a first conductivity type and an epitaxial layer of the same conductivity type that is applied to the substrate. At least two trenches are introduced into the epitaxial layer. The epitaxial layer is a stepped epitaxial layer that has two partial layers of different doping concentrations.
    Type: Application
    Filed: December 14, 2011
    Publication date: February 6, 2014
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8624347
    Abstract: A Schottky barrier diode includes a semiconductor layer having a plurality of trenches formed by digging in from a top surface and having mesa portions formed between adjacent trenches, and a Schottky metal formed to contact the top surface of the semiconductor layer including inner surfaces of the trenches.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: January 7, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshiteru Nagai, Kohei Makita
  • Patent number: 8617976
    Abstract: A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8604583
    Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
  • Publication number: 20130299937
    Abstract: A method and apparatus for reducing external series resistance (Rext) has been becoming a more dominant component of the total series resistance between the MOSFET source and drain. A significant part of Rext (25-35%) comes from the interface resistance (RC) between the metal (silicide) and source/drain (S/D) silicon diffusion regions. RC is determined by the specific contact resistivity (?c) at the silicide/silicon interface, the S/D silicon sheet resistivity at the silicide/silicon interface (RS/D), and the contact length (LC). The LC has been and will be decreasing by about 30% from one CMOS technology node to the next, resulting in increased RC and Rext. To maintain or reduce RC with respect to state-of-the-art value, one must reduce ?c. This may be accomplished using a metal-dopant alloy having a dopant material that can diffuse into the semiconductor layer during annealing to provide contact and ultralow resistance at the interface.
    Type: Application
    Filed: April 26, 2013
    Publication date: November 14, 2013
    Applicant: Applied Materials, Inc.
    Inventor: Khaled AHMED
  • Patent number: 8519429
    Abstract: The present invention provides a sealant for an optical semiconductor device which is less likely to reduce its luminance and is also less likely to change its color even used in an energized state in harsh environments of high temperature and high humidity. The sealant for an optical semiconductor device includes: a first organopolysiloxane not containing a hydrogen atom bound to a silicon atom, but containing an alkenyl group bound to a silicon atom and an aryl group bound to a silicon atom, a second organopolysiloxane containing a hydrogen atom bound to a silicon atom and an aryl group bound to a silicon atom, and a platinum-alkenyl complex. The platinum-alkenyl complex is a reaction product obtained by reacting chloroplatinic acid hexahydrate with not less than 6 equivalent of a bi- or more-functional alkenyl compound.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: August 27, 2013
    Assignee: Sekisui Chemical Co., Ltd.
    Inventors: Mitsuru Tanikawa, Takashi Watanabe, Shintaro Moriguchi, Osamu Inui, Yoshitaka Kunihiro, Ryosuke Yamazaki, Ayuko Oki
  • Patent number: 8487396
    Abstract: A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventor: Massimo Cataldo Mazzillo
  • Publication number: 20130140585
    Abstract: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.
    Type: Application
    Filed: January 28, 2013
    Publication date: June 6, 2013
    Applicant: Power Integrations, Inc.
    Inventor: Power Integrations, Inc.
  • Patent number: 8455322
    Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Rajendran Krishnasamy, Kathryn T. Schonenberg
  • Patent number: 8421179
    Abstract: A Schottky diode with high antistatic capability has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: April 16, 2013
    Assignee: Pynmax Technology Co., Ltd.
    Inventors: Chiun-Yen Tung, Kun-Hsien Chen, Kai-Ying Wang, Wen-Li Tsai
  • Patent number: 8415761
    Abstract: Exemplary embodiments of the invention include a thermoelectric material having an aligned polarization field along a central axis of the material. Along the axis are a first atomic plane and a second atomic plane of substantially similar area. The planes define a first volume and form a single anisotropic crystal. The first volume has a first outer surface and a second outer surface opposite the first outer surface, with the outer surfaces defining the central axis passing through a bulk. The bulk polarization field is formed from a first electrical sheet charge and a second opposing electrical sheet charge, one on each atomic plane. The opposing sheet charges define a bulk polarization field aligned with the central axis, and the bulk polarization field causes asymmetric thermal and electrical conductivity through the first volume along the central axis.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: April 9, 2013
    Assignee: Carrier Corporation
    Inventor: Joseph V. Mantese
  • Publication number: 20130062620
    Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.
    Type: Application
    Filed: September 11, 2011
    Publication date: March 14, 2013
    Applicant: CREE, INC.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 8384182
    Abstract: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: February 26, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Michael S. Mazzola, Lin Cheng
  • Patent number: 8378495
    Abstract: An IC includes a substrate having a semiconductor top surface, a plurality of metal interconnect levels having inter-level dielectric (ILD) layers therebetween on the top surface, and a bottom surface. A plurality of through substrate vias (TSVs) extend from a TSV terminating metal interconnect level downward to the bottom surface. The plurality of TSVs include an electrically conductive filler material surrounded by a dielectric liner that define a projected volume. The projected volume includes a projected area over the electrically conductive filler material and a projected height extending upwards from the TSV terminating metal interconnect level to a metal interconnect level above, and a projected sidewall surface along sidewalls of the projected volume. A crack suppression structure (CSS) protects TSVs and includes a lateral CSS portion that is positioned lateral to the projected volume and encloses at least 80% of the projected sidewall surface.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: February 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey A West