Plural Schottky Barriers With Different Barrier Heights Patents (Class 257/478)
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Patent number: 11946879Abstract: A thin film has a band gap of 2.2 eV or more and in which a crystal includes an atomic vacancy and an electron, a microwave irradiation system configured to irradiate the thin film with a microwave in response to driving from outside, an excitation unit configured to excite the electron included in the thin film in response to driving from outside, and a detector configured to detect, as an electric signal, at least either one of an intensity of light outputted from the thin film when the electron transitions from an excited state to a ground state and a change in conductivity of the thin film based on excitation.Type: GrantFiled: September 13, 2019Date of Patent: April 2, 2024Assignee: TOKYO INSTITUTE OF TECHNOLOGYInventors: Mutsuko Hatano, Takayuki Iwasaki, Nobuhiko Nishiyama, Yuta Masuyama, Takuya Murooka
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Patent number: 11575007Abstract: A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.Type: GrantFiled: September 24, 2021Date of Patent: February 7, 2023Assignee: II-VI DELAWARE, INC.Inventors: Hossein Elahipanah, Nicolas Thierry-Jebali, Adolf Schöner, Sergey Reshanov
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Patent number: 11011619Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.Type: GrantFiled: September 6, 2019Date of Patent: May 18, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
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Patent number: 10141262Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.Type: GrantFiled: May 9, 2018Date of Patent: November 27, 2018Assignee: Micron Technology, Inc.Inventor: Gurtej S. Sandhu
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Patent number: 9960247Abstract: A method for fabricating a silicon carbide power device may include steps of: forming a first n-type silicon carbide layer on top of a second n-type silicon carbide layer; depositing a first metal layer on the first silicon carbide layer; patterning the first metal layer; depositing and patterning a dielectric layer onto at least a portion of the pattered first metal layer; and depositing and patterning a second metal layer to form a Schottky barrier. In one embodiment, the first metal layer is a high work function metal layer, which may include Silver, Aluminum, Chromium, Nickel and Gold. In another embodiment, the second metal layer is called a “Schottky metal” layer, which may include Platinum, Titanium and Nickel Silicide.Type: GrantFiled: January 19, 2017Date of Patent: May 1, 2018Inventors: Ruigang Li, Zheng Zuo, Bochao Huang, Da Teng
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Patent number: 9659813Abstract: An interconnection includes first and second conductive layers, first and second dielectric layers, a stop layer, and first and second adhesion layers is provided. The first conductive layer is disposed over a semiconductor substrate. The first dielectric layer is over the first conductive layer, and the first dielectric layer includes a via hole. The second dielectric layer is disposed over the first dielectric layer. The stop layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the stop layer include a trench. The second conductive layer is located in the via hole and the trench to electrically connect with the first conductive layer. The first adhesion layer is located on sidewalls of the trench. The second adhesion layer is located between the second conductive layer and the first adhesion layer and between the second conductive layer and the first dielectric layer.Type: GrantFiled: March 16, 2016Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
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Patent number: 9041142Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.Type: GrantFiled: December 11, 2012Date of Patent: May 26, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ying-Chieh Tsai, Wing-Chor Chan, Jeng Gong
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Patent number: 8957476Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.Type: GrantFiled: December 20, 2012Date of Patent: February 17, 2015Assignee: Intel CorporationInventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
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Patent number: 8901612Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.Type: GrantFiled: February 24, 2012Date of Patent: December 2, 2014Assignees: Phononic Devices, Inc., The Board of Regents of the University of OklahomaInventors: Allen L. Gray, Robert Joseph Therrien, Patrick John McCann
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Patent number: 8896085Abstract: A semiconductor light-emitting element manufacturing method including: a first step in which a first n-type semiconductor layer is laminated onto a substrate in a first organometallic chemical vapor deposition apparatus; and a second step in which a regrowth layer, a second n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially laminated onto the aforementioned first n-type semiconductor layer in a second organometallic chemical vapor deposition apparatus.Type: GrantFiled: July 9, 2010Date of Patent: November 25, 2014Assignee: Toyoda Gosei Co., Ltd.Inventor: Hiromitsu Sakai
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Patent number: 8896084Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.Type: GrantFiled: February 23, 2011Date of Patent: November 25, 2014Assignees: Fuji Electric Co., Ltd.Inventor: Yoshitaka Sugawara
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Patent number: 8823128Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.Type: GrantFiled: May 13, 2011Date of Patent: September 2, 2014Assignee: Macronix International Co., Ltd.Inventors: Wing-Chor Chan, Hsin-Liang Chen
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Patent number: 8796808Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.Type: GrantFiled: April 21, 2009Date of Patent: August 5, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
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Patent number: 8723296Abstract: A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.Type: GrantFiled: November 30, 2010Date of Patent: May 13, 2014Assignee: National Semiconductor CorporationInventor: Jamal Ramdani
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Patent number: 8716863Abstract: The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer.Type: GrantFiled: July 13, 2011Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsingjen Wann, Ting-Chu Ko
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Patent number: 8664740Abstract: A semiconductor device improves a Schottky-barrier field-effect transistor. In a semiconductor device including a gate electrode formed with interposition of a gate insulating film on a channel formed on a semiconductor substrate, and a Schottky source/drain formed within a top surface of the substrate to be positioned on both sides of the gate insulating film so that end portions of the Schottky source and the Schottky drain do not cover a lower end portion of the gate insulating film and so as to form Schottky junctions with the semiconductor substrate, a Schottky barrier height at an interface between the end portion of the Schottky source and the semiconductor substrate and a Schottky barrier height at an interface between the end portion of the Schottky drain and the semiconductor substrate are different from Schottky barrier heights at interfaces between portions except the end portions of the Schottky source/drain and the substrate.Type: GrantFiled: April 16, 2009Date of Patent: March 4, 2014Assignee: Renesas Electronics CorporationInventor: Kenzo Manabe
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Patent number: 8633561Abstract: A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.Type: GrantFiled: February 9, 2010Date of Patent: January 21, 2014Assignee: Siliconix Technology C. V.Inventors: Ali Husain, Srinkant Sridevan
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Patent number: 8629426Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.Type: GrantFiled: December 3, 2010Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hsiang Lin, Jeff J. Xu, Pang-Yen Tsai
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Patent number: 8536036Abstract: In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.Type: GrantFiled: October 15, 2010Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Jan Hoentschel, Uwe Griebenow, Thilo Scheiper
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Patent number: 8426939Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer.Type: GrantFiled: January 8, 2010Date of Patent: April 23, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8421180Abstract: A semiconductor structure is provided. A second area is disposed between first and third areas. An epitaxial layer is on a substrate. A body layer is in the epitaxial layer in first and second areas. First and second gates are in the body layer and in a portion of the epitaxial layer. The first gate is in the substrate and partially in first and second areas. The second gate is in the substrate and partially in second and third areas. A first contact plug is in a portion of the body layer in the first area. A second contact plug is at least in the epitaxial layer in the third area and contacts the epitaxial layer and the second gate. The first contact plug is electrically connected to the second contact plug. A first doped region is in the body layer between the first contact plug and the first gate.Type: GrantFiled: May 25, 2012Date of Patent: April 16, 2013Assignee: Excelliance MOS CorporationInventor: Chu-Kuang Liu
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Patent number: 8373245Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.Type: GrantFiled: January 8, 2010Date of Patent: February 12, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8319310Abstract: A Schottky gate (27?, 27?) of a metal-semiconductor FET (20?, 20?) is formed on a semiconductor comprising substrate (21) by, etching a gate recess (36) so as to expose a slightly depressed surface (362) of the substrate (21), the etching step also producing surface undercut cavities (363) extending laterally under the etch mask (43) from the gate recess (36), then conformally coating the slightly depressed surface (362) with a first Schottky forming conductor (40?) and substantially also coating inner surfaces (366) of the surface undercut cavities (363), and forming a Schottky contact to the semiconductor comprising substrate (21), adapted when biased to control current flow in a channel (22) extending between source (23) and drain (24) of the FET (20?, 20?) under the gate recess (36).Type: GrantFiled: March 31, 2009Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Jenn Hwa Huang
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Patent number: 8198687Abstract: A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween.Type: GrantFiled: May 13, 2010Date of Patent: June 12, 2012Assignee: Fairchild Semiconductor CorporationInventor: Mark Rinehimer
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Patent number: 8183660Abstract: A semiconductor component is proposed which has a semiconductor body having a first semiconductor zone of the first conduction type, at least one first rectifying junction with respect to the first semiconductor zone, at least one second rectifying junction with respect to the first semiconductor zone, wherein the three rectifying junctions each have a barrier height of different magnitude.Type: GrantFiled: February 26, 2008Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Michael Rueb, Roland Rupp, Michael Treu
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Patent number: 8173540Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: October 14, 2010Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 8125008Abstract: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.Type: GrantFiled: November 17, 2006Date of Patent: February 28, 2012Assignee: System General CorporationInventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin
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Patent number: 7964930Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.Type: GrantFiled: September 13, 2005Date of Patent: June 21, 2011Assignee: Robert Bosch GmbHInventors: Alfred Goerlach, Ning Qu
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Patent number: 7880174Abstract: An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is formed by connecting a silicon PiN diode in parallel with a Schottky barrier diode that uses a semiconductor material having a wider band gap than silicon as a base material. The silicon PiN diode and Schottky barrier diode are separate chips.Type: GrantFiled: February 12, 2008Date of Patent: February 1, 2011Assignee: Hitachi, Ltd.Inventors: Haruka Shimizu, Katsumi Ishikawa, Masahiro Nagasu, Dai Tsugawa
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Patent number: 7829970Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.Type: GrantFiled: April 22, 2008Date of Patent: November 9, 2010Assignee: Intersil Americas Inc.Inventors: Dev Alok Girdhar, Michael David Church
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Patent number: 7750427Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.Type: GrantFiled: January 6, 2009Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
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Patent number: 7750412Abstract: A structure that includes a rectifier is formed as follows. A trench is formed in a semiconductor region of a first conductivity type. A dielectric layer is formed along opposing sidewalls of the trench but is discontinuous along the bottom of the trench. A doped liner is formed over the dielectric layer and along the bottom of the trench. The doped liner includes dopants of a second conductivity type and is in direct contact with the semiconductor region along the bottom of the trench. A portion of the dopants are diffused from the doped liner into the semiconductor region along the bottom of the trench to form a doped region. The doped region forms a PN junction with the surrounding semiconductor region.Type: GrantFiled: August 6, 2008Date of Patent: July 6, 2010Assignee: Fairchild Semiconductor CorporationInventor: Mark Rinehimer
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Patent number: 7745878Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.Type: GrantFiled: November 18, 2008Date of Patent: June 29, 2010Assignee: Alpha & Omega Semiconductor, LtdInventors: Anup Bhalla, Sik K Lui
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Patent number: 7528459Abstract: A monolithically integrated punch-through diode with a Schottky-like behavior. This is achieved as a Schottky-metal area (16) is deposited onto at least part of the first p-doped well's (9) surface. The Schottky-metal area (16) and the p-doped well (9) form the metal-semiconductor-transition of a Schottky-diode. The overvoltage protection of the inventive PT-diode is improved as the forward characteristic has a voltage drop that is less than 0.5V.Type: GrantFiled: May 24, 2004Date of Patent: May 5, 2009Assignee: NXP B.V.Inventors: Hans-Martin Ritter, Martin Lübbe, Jochen Wynants
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Publication number: 20070296052Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: June 26, 2006Publication date: December 27, 2007Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 7164183Abstract: A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress to it.Type: GrantFiled: June 2, 2004Date of Patent: January 16, 2007Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Nobuhiko Sato
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Patent number: 6972470Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.Type: GrantFiled: March 30, 2004Date of Patent: December 6, 2005Assignee: Texas Instruments IncorporatedInventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
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Patent number: 6787871Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: GrantFiled: October 30, 2002Date of Patent: September 7, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6764918Abstract: A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material (81) reduces diffusion of dopants in the base region during subsequent thermal processing.Type: GrantFiled: December 2, 2002Date of Patent: July 20, 2004Assignee: Semiconductor Components Industries, L.L.C.Inventor: Gary H. Loechelt
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Patent number: 6734515Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).Type: GrantFiled: March 16, 2001Date of Patent: May 11, 2004Assignees: Mitsubishi Cable Industries, Ltd., Nikon CorporationInventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Youichiro Ohuchi, Masahiro Koto, Kazumasa Hiramatsu, Yutaka Hamamura, Sumito Shimizu
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Patent number: 6670650Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.Type: GrantFiled: August 2, 2002Date of Patent: December 30, 2003Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Tatsuya Naito, Masahito Otsuki, Mitsuaki Kirisawa
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Publication number: 20030094673Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.Type: ApplicationFiled: November 16, 2001Publication date: May 22, 2003Applicant: International Business Machines CorporationInventors: James S. Dunn, Louis D. Lanzerotti, Steven H. Voldman
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Patent number: 6483164Abstract: A Schottky electrode is formed of an alloy, which is composed of two or more kinds of metal materials in combinations that provide different Schottky barrier heights with respect to a semiconductor and that form no intermetallic compound.Type: GrantFiled: July 7, 2000Date of Patent: November 19, 2002Assignee: Fuji Electric Co., Ltd.Inventors: Hiroshi Kanemaru, Shinji Ogino
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Patent number: 6462393Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.Type: GrantFiled: March 20, 2001Date of Patent: October 8, 2002Assignee: FabTech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
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Publication number: 20010023972Abstract: Polymer blobs that are development related defects are substantially eliminated in the patterned photoresist masks by a heat treatment of the wafer performed at the development step in two different manners according to the present invention. In the first method, after the development has been performed as standard, the wafer is heated at 140° C. and before cooling takes place, it is rinsed with deionized water (DIW) at room temperature. In the second method, the wafer is either developed as standard but rinsed with 60° C. DIW instead of 22° C. DIW or, after standard development, it is submitted to an extra rinse step with 60° C. DIW.Type: ApplicationFiled: January 8, 2001Publication date: September 27, 2001Inventor: Caroline Boulenger
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Patent number: 6104043Abstract: A Schottky diode of SiC has a substrate layer, a drift layer and emitter layer regions formed in the drift layer. A metal layer makes an ohmic contact to the emitter layer regions and Schottky contact to the drift layer. A depletion of the drift layer region between two adjacent emitter layer regions is allowed in the blocking state of the diode making the two adjacent p-type emitter layer regions form a continuous depleted region therebetween in this state.Type: GrantFiled: February 20, 1997Date of Patent: August 15, 2000Assignee: ABB Research Ltd.Inventors: Willy Hermansson, Bo Bijlenga, Lennart Ramberg, Kurt Rottner, Lennart Zdansky, Christopher Ian Harris, Mietek Bakowski, Adolf Schoner, Nils Lundberg, Mikael Ostling, Fanny Dahlquist
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Patent number: 6087704Abstract: Group III-V composites, which is used to manufacture Schottky contacts having the characteristics of higher energy gap, higher carriers mobility, etc., are applied for manufacturing high-speed devices. Therefore, in there years, Group III-V composite Schottky contacts are continuously being developed. In the invention, the surface treatment of composite semiconductor is used for reduce a surface state and oxidation, thereby increased the Schottky barriers of the Group III-V composite (such as, GaAs, InP, InAs and InSb) Schottky contacts. During experiments, a phosphorus sulphide/ammonia sulphide solution and hydrogen fluoride solution are used for the surface treatment to increase the amount of sulphur contained on the surfaces of substrates, reduce the surface state and remove various oxides. Furthermore, ultra-thin and really stable sulphur fluoride/phosphorus fluoride layers having high energy gaps are formed on various substrates.Type: GrantFiled: September 30, 1997Date of Patent: July 11, 2000Assignee: National Science CouncilInventors: Liann-Be Chang, Hung-Tsung Wang
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Patent number: 5930636Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.Type: GrantFiled: May 13, 1996Date of Patent: July 27, 1999Assignee: TRW Inc.Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
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Patent number: 5793670Abstract: A memory cell includes first and second driver transistors, first and second access transistors and first and second load elements, and in addition, first and second bipolar transistors. Accordingly, static noise margin is enlarged. The first bipolar transistor has its emitter formed in one of the source/drain regions of the first access transistor. The collector of the first bipolar transistor is the backgate terminal of the first access transistor. One of the source/drain regions of the first access transistor functions as the base of the first bipolar transistor. The same applies to the second bipolar transistor and the second access transistor. As the memory cell is structured in the above described manner, lower power supply potential can be used without the problem of latch up or increased area.Type: GrantFiled: October 21, 1996Date of Patent: August 11, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomohisa Wada, Hirotoshi Sato, Hiroki Honda
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Patent number: 5469103Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.Type: GrantFiled: March 22, 1994Date of Patent: November 21, 1995Assignee: Fuji Electric Co., Ltd.Inventor: Hisao Shigekane