In Integrated Structure Patents (Class 257/476)
  • Patent number: 10797181
    Abstract: A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×1020 cm?3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 6, 2020
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tomoyoshi Mishima, Fumimasa Horikiri
  • Patent number: 10741699
    Abstract: A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 11, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Taiji Ema, Makoto Yasuda
  • Patent number: 10658524
    Abstract: A Schottky barrier diode includes a semiconductor layer having a major surface, a diode region of a first conductivity type formed in a surface layer portion of the semiconductor layer, a first conductivity type impurity region formed in the surface layer portion of the semiconductor layer and electrically connected to the diode region, a first electrode layer formed on the major surface of the semiconductor layer and forming a Schottky junction with the diode region, a second electrode layer formed on the major surface of the semiconductor layer and forming an ohmic junction with the first conductivity type impurity region, and a contact electrode layer formed on a peripheral region of the major surface of the semiconductor layer surrounding the first electrode layer so as to be electrically connected to the diode region via the semiconductor layer and being electrically connected to the second electrode layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 19, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 10608122
    Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the doped region with the multi-concentration impurity profile.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 31, 2020
    Assignee: SEMICONDUTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Jefferson W. Hall
  • Patent number: 10580906
    Abstract: A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 3, 2020
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Marina Vroubel, Paul Alexander Grudowski
  • Patent number: 10535783
    Abstract: One embodiment of the disclosure relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vladimir Frank Drobny
  • Patent number: 10370790
    Abstract: A textile article includes a first fabric including a plurality of first carbon nanotubes coupled to the first fabric. The first carbon nanotubes of the plurality of first carbon nanotubes are metallic carbon nanotubes. A second fabric includes a plurality of second carbon nanotubes coupled to the second fabric. The second carbon nanotubes of the plurality of second carbon nanotubes are semiconductive carbon nanotubes. The first fabric is interconnected with the second fabric.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abram L. Falk, Shu-Jen Han, Bharat Kumar
  • Patent number: 10192960
    Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 29, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
  • Patent number: 9842911
    Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: December 12, 2017
    Assignee: Vishay-Siliconix
    Inventors: Naveen Tipirneni, Deva N. Pattanayak
  • Patent number: 9754960
    Abstract: Provided herein is a semiconductor memory device including: a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array. The peripheral circuit includes a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit. The power decoupling capacitor circuit includes conductive lines which are alternately stacked on top of one another, a plurality of semiconductor pillars configured to pass through the conductive lines, a horizontal connector configured to connect the semiconductor pillars to each other, and a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 5, 2017
    Assignee: SK hynix Inc.
    Inventor: Jae Eun Jeon
  • Patent number: 9685442
    Abstract: A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 20, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Makoto Yasuda, Mitsuaki Hori
  • Patent number: 9659927
    Abstract: A junction barrier Schottky rectifier with first and second drift layer sections, wherein a peak net doping concentration of the first section is at least two times lower than a minimum net doping concentration of the second section. For each emitter region the first section includes a layer which is in contact with the respective emitter region to form a pn-junction between the first section and the respective emitter region, wherein the thickness of this layer in a direction perpendicular to the interface between the first section and the respective emitter region is at least 0.1 ?m. The JBS rectifier has a transition from unipolar to bipolar conduction mode at a lower forward bias due to lowering of electrostatic forces otherwise impairing the transport of electrons toward the emitter regions under forward bias conditions, and with reduced snap-back phenomenon.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 23, 2017
    Assignee: ABB Schweiz AG
    Inventors: Friedhelm Bauer, Andrei Mihaila
  • Patent number: 9564516
    Abstract: A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: February 7, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Ji Pan
  • Patent number: 9548292
    Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: January 17, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Patent number: 9443912
    Abstract: There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 13, 2016
    Assignee: Sony Corporation
    Inventors: Keisuke Hatano, Tetsuji Yamaguchi, Shintarou Hirata
  • Patent number: 9406661
    Abstract: A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 2, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 9391119
    Abstract: Embodiments of non-volatile random access memory (RAM) devices and methods of forming the same are provided herein. In an embodiment, a non-volatile RAM device includes a first access transistor that is in electrical communication with a wordline. A first memory element and a first two-terminal selector are serially connected to each other and are in electrical communication with a first bitline and the first access transistor. A second memory element and a second two-terminal selector are serially connected to each other and are in electrical communication with a second bitline and the first access transistor.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: An Chen
  • Patent number: 9306113
    Abstract: A light emitting device comprises a body of an indirect bandgap semiconductor material. A junction region is formed between a first region in the body of a first doping kind and a second region of the body of a second doping kind of first concentration. A third region of the second doping kind of a second concentration is spaced from the junction region by the second region. The second concentration is higher than the first concentration. A terminal arrangement is connected to the body for, in use, reverse biasing the first junction region into a breakdown mode, thereby to cause emission of light. The device is configured such that a depletion region associated with the junction region reaches through the shaped region to reach the third region, before the junction enters the breakdown mode.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: April 5, 2016
    Assignee: INSIAVA (PTY) LIMITED
    Inventor: Monuko Du Plessis
  • Patent number: 9269774
    Abstract: An electronic device (1) includes a semiconductor substrate (3) having a front surface (7), a first electrode (8) and a second electrode (9) disposed on the front surface (7) of the substrate (3), wherein the first electrode (8) and the second electrode (9) each have at least one epitaxial graphene monolayer (10). The at least one epitaxial graphene monolayer (10) of the first electrode (8) forms an ohmic contact with the substrate (3) and the at least one epitaxial graphene monolayer (10) of the second electrode (9) forms a Schottky barrier with the substrate (3).
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 23, 2016
    Assignee: Friedrich-Alexander-Universität Erlangen-Nürnberg
    Inventors: Heiko B. Weber, Michael Krieger, Stefan Hertel, Florian Krach, Johannes Jobst, Daniel Waldmann
  • Patent number: 9260174
    Abstract: An apparatus includes a first component that has a first coefficient of thermal expansion, a fastener that extends at least partially through the first component. The fastener has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The apparatus also includes a nano-tube mesh coupled to outer surfaces of the first component and fastener. Further, the apparatus includes a second component applied to the nano-tube mesh and outer surface of the first component. The nano-tube mesh may include carbon nano-tubes and/or nitrogen-doped carbon nano-tubes.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: February 16, 2016
    Assignee: The Boeing Company
    Inventor: Morteza Safai
  • Patent number: 9257420
    Abstract: An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 9, 2016
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Aurelie Arnaud
  • Patent number: 9257915
    Abstract: A bridge rectifier circuit has first to fourth diode groups which are bridge-connected and each include a main diode and sub-diodes being enabled to be respectively connected in parallel to the main diode, first and second input terminals to which AC power is supplied, a first output terminal connected to the first input terminal via the first diode group and connected to the second input terminal via the second diode group, a second output terminal connected to the first input terminal via the third diode group and connected to the second input terminal via the fourth diode group, and a control circuit configured to detect a current flowing through at least one diode group and increases the number of sub-diodes connected in parallel to the main diode of the diode group through which the detected current flows in accordance with an increase in the detected current.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: February 9, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Hideta Oki, Yukinori Maekawa
  • Patent number: 9245754
    Abstract: A method of forming a charge balance region in an active semiconductor device includes: forming an epitaxial region including material of a first conductivity type on an upper surface of a substrate of the semiconductor device; forming multiple recessed features at least partially through the epitaxial region; depositing a film comprising material of a second conductivity type on a bottom and/or sidewalls of the recessed features using atomic layer deposition; and performing thermal processing such that at least a portion of the film deposited on the bottom and/or sidewalls of each of the recessed features forms a region of the second conductivity type in the epitaxial layer which follows a contour of the recessed features, the region of the second conductivity type, in conjunction with the epitaxial layer proximate the region of the second conductivity type, forming the charge balance region.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 26, 2016
    Inventor: Mark E. Granahan
  • Patent number: 9087704
    Abstract: According to example embodiments, a semiconductor device may include a high electron mobility transistor (HEMT) on a first region of a substrate, and a diode on a second region of the substrate. The HEMT may be electrically connected to the diode. The HEMT and the diode may be formed on an upper surface of the substrate such as to be spaced apart from each other in a horizontal direction. The HEMT may include a semiconductor layer. The diode may be formed on another portion of the substrate on which the semiconductor layer is not formed. The HEMT and the diode may be cascode-connected to each other.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-chul Jeon, Young-hwan Park, Ki-yeol Park, Jai-kwang Shin, Jae-joo Oh, Jong-bong Ha
  • Patent number: 9041142
    Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 26, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ying-Chieh Tsai, Wing-Chor Chan, Jeng Gong
  • Patent number: 9018672
    Abstract: Provided is a semiconductor device including: a semiconductor element arranged on a substrate and having two electrodes; a conductive strip in contact with one of the two electrodes; and a dielectric arranged between another one of the two electrodes and the conductive strip, in which the conductive strip has an opening formed therein, the dielectric has a void formed therein, and the opening and the void are connected to each other.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryota Sekiguchi, Alexis Debray, Yasushi Koyama, Kosuke Asano, Satoshi Yokoyama, Atsushi Kemmochi
  • Publication number: 20150102451
    Abstract: Methods and devices associated with a phase change memory include Schottky diodes operating as selectors having a low turn-on voltage, low sneak current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate having a diode array region and a peripheral device region, forming an N+ buried layer in the diode array region, forming a semiconductor epitaxial layer on the N+ buried layer, and forming deep trench isolations through the epitaxial layer and the N+ buried layer along a first direction. The method also includes forming shallow trench isolations in the diode array region and in the peripheral region along a second line direction. The method also includes forming an N? doped region between the deep and shallow trench isolations and forming a metal silicide on a surface of the N? doped region.
    Type: Application
    Filed: March 7, 2014
    Publication date: April 16, 2015
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: CHAO ZHANG
  • Patent number: 9000550
    Abstract: A semiconductor component having a low resistance conduction path and a method for manufacturing the semiconductor component. When the semiconductor component is a Schottky diode, one or more trenches are formed in an epitaxial layer of a first conductivity type that is formed over a semiconductor substrate of the first conductivity type. The trenches may extend into the semiconductor material. Epitaxial semiconductor material of a second conductivity type is selectively grown along the sidewalls of the trenches. An anode contact is formed in contact with the epitaxial layer and the selectively grown epitaxial material and a cathode contact is formed in contact with the semiconductor substrate.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Mohammed Tanvir Quddus
  • Patent number: 8969993
    Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8969995
    Abstract: High-efficiency Schottky diodes (HED) and rectifier systems having such semiconductor devices are provided, which Schottky diodes (HED) are composed of at least one Schottky diode combined with an additional semiconductor element, e.g., with magnetoresistors (TMBS) or with pn diodes (TJBS), and have trenches. Such high-efficiency Schottky diodes make it possible to construct rectifiers which are suitable for higher temperatures and can therefore be used in motor vehicle generators, without particular cooling measures such as heat sinks being required.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Gert Wolf, Markus Mueller
  • Publication number: 20150054116
    Abstract: A high voltage device having Schottky diode includes a semiconductor substrate, a Schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the Schottky diode, and a control gate positioned on the semiconductor substrate. The control gate covers a portion of the Schottky diode and the first doped region positioned on the semiconductor substrate.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 26, 2015
    Inventor: Min-Hsuan Tsai
  • Patent number: 8963275
    Abstract: A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element (40) and a Schottky diode (30). The Schottky diode (30) and the resistive-switching element (40) are connected in series. The Schottky diode (30) includes a metal layer and a semiconductor layer contacting each other. An interface between the metal layer and the semiconductor layer has a non-planar shape.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 24, 2015
    Assignee: Peking University
    Inventors: Jinfeng Kang, Bin Gao, Lifeng Liu, Xiaoyan Liu
  • Patent number: 8957461
    Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomonori Mizushima, Michio Nemoto
  • Publication number: 20150021732
    Abstract: A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a Schottky barrier diode formed in the first well; and a PN junction diode formed in the second well, with an impurity concentration of the PN junction thereof set higher than an impurity concentration of the Schottky junction of the Schottky barrier diode, and being connected antiparallel with the Schottky barrier diode.
    Type: Application
    Filed: June 17, 2014
    Publication date: January 22, 2015
    Inventors: Dai Kanai, Taiji Ema, Kazushi Fujita
  • Patent number: 8921969
    Abstract: A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: December 30, 2014
    Assignee: Siliconix Technology C. V.
    Inventor: Slawomir Skocki
  • Patent number: 8878329
    Abstract: A high voltage device having a Schottky diode integrated with a MOS transistor includes a semiconductor substrate a Schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the Schottky diode, and a control gate covering a portion of the Schottky diode and the first doped region positioned on the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 4, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Min-Hsuan Tsai
  • Publication number: 20140319644
    Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 30, 2014
    Inventors: Gordon M. Grivna, Jefferson W. Hall, Mohammed Tanvir Quddus
  • Patent number: 8860168
    Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 8860169
    Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
  • Patent number: 8836072
    Abstract: A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 16, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8823128
    Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: September 2, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Wing-Chor Chan, Hsin-Liang Chen
  • Publication number: 20140239435
    Abstract: A semiconductor chip has an n+-doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a Schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions. A second metal layer which represents an ohmic contact and functioning as a cathode is formed on the rear side of the semiconductor chip. A dielectric layer is provided between each n-doped region and an adjacent p-doped region.
    Type: Application
    Filed: July 19, 2012
    Publication date: August 28, 2014
    Inventors: Ning Qu, Alfred Goerlach
  • Publication number: 20140197515
    Abstract: A high voltage circuit layout structure has a P-type substrate; a first N-type tub, a second N-type tub, a third N-type tub, a first P-type tub with a first width and a second P-type tub with a second width formed on the P-type substrate; wherein the first P-type tub is formed between the first N-type tub and the second N-type tub; and the second P-type tub is formed between the second N-type tub and the third N-type tub.
    Type: Application
    Filed: January 17, 2013
    Publication date: July 17, 2014
    Applicant: MONOLITHIC POWER SYSTEMS, INC.
    Inventor: Joseph Urienza
  • Patent number: 8759937
    Abstract: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 24, 2014
    Assignee: Synopsys, Inc.
    Inventors: Yanjun Ma, Ronald A. Oliver, Todd E. Humes, Jaideep Mavoori
  • Patent number: 8736012
    Abstract: A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventors: Chao-Hsin Huang, Chih-Chiang Chuang
  • Patent number: 8716825
    Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: May 6, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Wing-Chor Chan, Chung-Yu Hung, Chien-Wen Chu
  • Patent number: 8669614
    Abstract: A monolithic metal oxide semiconductor field effect transistor (MOSFET)-Schottky diode device including a chip, a MOSFET, a Schottky diode and a termination structure is provided. The chip is divided into a transistor region, a diode region and a termination region. The MOSFET is disposed on the transistor region. The Schottky diode is disposed on the diode region. The termination structure is disposed on the termination region. The transistor region and the diode region are divided by the termination region. The MOSFET and Schottky diode share the termination structure.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: March 11, 2014
    Assignee: Beyond Innovation Technology Co., Ltd.
    Inventor: Chien-Hsing Cheng
  • Publication number: 20140061848
    Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Publication number: 20140061731
    Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 8653589
    Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 18, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh