Microwave Transit Time Device (e.g., Impatt Diode) Patents (Class 257/482)
  • Patent number: 9472585
    Abstract: A semiconductor package includes: a sheet-like thin plate on which a semiconductor chip is secured; and a substrate including a wiring layer, disposed on the thin plate to extend over a part of a region surrounding the region where the semiconductor chip is secured or over the entire surrounding region, wherein the semiconductor chip and the substrate are electrically connected.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 18, 2016
    Inventor: Masayuki Ishikida
  • Patent number: 9324801
    Abstract: Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8890277
    Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: November 18, 2014
    Assignee: University of Florida Research Foundation Inc.
    Inventors: Arthur Foster Hebard, Sefaattin Tongay
  • Patent number: 8878276
    Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 8803298
    Abstract: With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Shingo Eguchi
  • Patent number: 8716121
    Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1-x-y)Si(x)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 6, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Masahiro Sugimoto, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Patent number: 8587094
    Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Kawasaki
  • Patent number: 8492866
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Patent number: 8227855
    Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: July 24, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph Yedinak, Mark Rinehimer, Thomas E. Grebs, John Benjamin
  • Patent number: 8212281
    Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: July 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 8212327
    Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 3, 2012
    Assignee: SiOnyx, Inc.
    Inventors: Neal T. Kurfiss, James E. Carey, Xia Li
  • Patent number: 8044486
    Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 25, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: François Hébert
  • Patent number: 7829970
    Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: November 9, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Dev Alok Girdhar, Michael David Church
  • Patent number: 7812368
    Abstract: The invention relates to a high-speed diode comprising a semiconductor body (1), in which a heavily n-doped zone (8), a weakly n-doped zone (7) and a weakly p-doped zone (6) are arranged successively in a vertical direction (v), between which a pn load junction (4) is formed. A number of heavily p-doped islands (51-57) spaced apart from one another are arranged in the weakly p-doped zone (6). In this case, it is provided that the cross-sectional area density of the heavily p-doped islands (51-57) is smaller in a first area region (100) near to the edge than in a second area region (200) remote from the edge.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: October 12, 2010
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reiner Barthelmess
  • Patent number: 7750442
    Abstract: A high-frequency switch includes a semiconductor body made of a semiconductor material having a first surface and a second surface, and two direct current terminals and two high-frequency terminals.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 6, 2010
    Assignee: Infineon Technologies AG
    Inventor: Reinhard Gabl
  • Patent number: 7691688
    Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Meikei Ieong, Alexander Reznicek, Devendra K. Sadana, Leathen Shi, Min Yang
  • Patent number: 7638857
    Abstract: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: December 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yen Hwang, Shu-Hsuan Su, Tien-Hao Tang
  • Patent number: 7538367
    Abstract: The present invention provides an avalanche photodiode capable of raising productivity. An n-type InP buffer layer, an n-type GaInAs light absorption layer, an n-type GaInAsP transition layer, an n-type InP electric field adjusting layer, an n-type InP avalanche intensifying layer, an n-type AlInAs window layer and a p-type GaInAs contact layer are grown in order on an n-type InP substrate. Next, Be is ion-injected into an annular area along the outer periphery of a light receiving area which is activated by heat treatment so as to form an inclined joint, to obtain a p-type peripheral area for preventing an edge break down. Further, Zn is selectively diffused thermally into the light receiving area until it reaches the n-type InP avalanche intensifying layer so as to form a p-type conductive area.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: May 26, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiji Yagyu, Eitaro Ishimura, Masaharu Nakaji
  • Patent number: 7511357
    Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: March 31, 2009
    Assignee: Force-MOS Technology Corporation
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7071525
    Abstract: A Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: July 4, 2006
    Assignee: International Rectifier Corporation
    Inventors: Davide Chiola, Kohji Andoh, Silvestro Fimiani
  • Patent number: 7015556
    Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 ?mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: March 21, 2006
    Assignee: TDK Corporation
    Inventors: Masahiro Nakano, Katsuhiko Gunji, Yasunobu Oikawa, Katsuo Sato
  • Patent number: 7012337
    Abstract: A semiconductor device includes a substrate with a via hole. An electrode is formed on a surface of the substrate so that a portion of the electrode extends through the via hole. A photosensitive resin is formed over the surface so as to cover an aperture of the via hole.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanobu Nogome, Akiyoshi Tamura, Keiichi Murayama, Kazutsune Miyanaga, Yoshitaka Kuroishi
  • Patent number: 6936868
    Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: August 30, 2005
    Assignee: Anritsu Corporation
    Inventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
  • Patent number: 6921952
    Abstract: A torsion spring for a MEMS structure has a plurality of beams, each beam having two ends wherein both ends are fixed to a predetermined area, and at least one connection bar disposed at a right angle to a lengthwise direction of the plurality of beams, wherein the at least one connection bar connects the plurality of beams. Preferably, the distance between the connection bars is equal to or greater than the width of one of the plurality of beams. Accordingly, a torsion spring according to the present invention has a bending stiffness greater than a torsional stiffness, which allows easier torsion. Further, a torsion spring according to the present invention may be easily fabricated by etching.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: July 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hee-moon Jeong
  • Patent number: 6855587
    Abstract: A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: February 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Min-Hwa Chi
  • Patent number: 6759744
    Abstract: The electronic circuit unit of the present invention includes first and second insulating substrates on respective surfaces of which wiring patterns are formed, and thick-film passive elements formed on the surfaces of the first and second insulating substrates in a state in which they are connected to the wiring patterns, wherein the first and second insulating substrates are disposed vertically opposite to each other, and the wiring patterns provided on the first and second insulating substrates are connected through metallic bumps provided between the first and second insulating substrates.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: July 6, 2004
    Assignee: Alps Electric Co., Ltd.
    Inventor: Yoshitaka Hirose
  • Publication number: 20030224549
    Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.
    Type: Application
    Filed: January 8, 2003
    Publication date: December 4, 2003
    Inventors: Joel N. Schulman, David H. Chow
  • Publication number: 20020140088
    Abstract: A semiconductor integrated circuit has a 3-dimmensional interconnection line structure for high-speed operation. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a 3-dimmensional tournament tree shaped multilayer interconnection lines, wherein a single electric feeding point on a top surface of the MMIC is divided, layer by layer, into plural electrodes on the semiconductor substrate of the MMIC via a plurality of laminated interconnection layers and vertical interconnection layers therebetween shaped like a tournament tree.
    Type: Application
    Filed: March 1, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Publication number: 20020020893
    Abstract: A monolithic assembly of a vertical fast diode with at least one additional vertical component, in which the fast diode is formed by an N-type substrate in one surface of which an N+-type continuous region is formed and in the other surface of which a P+-type discontinuous region is formed. The bottom surface of the assembly is coated with a single metallization. The other vertical component is, for example, a diode.
    Type: Application
    Filed: June 6, 1996
    Publication date: February 21, 2002
    Inventor: ANDRE LHORTE
  • Patent number: 6274922
    Abstract: A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: August 14, 2001
    Assignee: Hughes Electronics Corporation
    Inventors: Debabani Choudhury, James A. Foschaar, Phillip H. Lawyer, David B. Rensch
  • Patent number: 6147386
    Abstract: A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: November 14, 2000
    Assignee: NEC Corporation
    Inventor: Tadahiko Horiuchi
  • Patent number: 6075276
    Abstract: A semiconductor device is provided which includes a first conductivity type semiconductor substrate, a second conductivity type Zener region formed in a surface layer of the first conductivity type semiconductor substrate, a first conductivity type anode region formed within the second conductivity type Zener region, an anode electrode which is formed in contact with both of the semiconductor substrate and first conductivity type anode region and is grounded, and a cathode electrode formed on a surface of the second conductivity type Zener region and connected to input and output terminals. A diode that consists of the first conductivity type semiconductor substrate and the second conductivity type Zener region and a diode that consists of the first conductivity type anode region and the second conductivity type Zener region serve as protective elements for preventing electrostatic breakdown of the semiconductor device.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 13, 2000
    Assignee: Fuji Electric Company, Ltd.
    Inventor: Akio Kitamura
  • Patent number: 6002147
    Abstract: The microwave hybrid integrated circuit comprises a dielectric board (1) provided with a topological metallization pattern (2) on its face side, a shield grounding metallization (3) on the back side thereof, a hole (4), and a metal base (5) having a projection (6). The hole (4) in the board (1) has a constriction (9) situated at a height of 1 to 300 .mu.m from the face surface of the board (1). The projection (6) is located in a wide section (10) of the hole (4). Bonding pads (8) of a chip (7) which are to be grounded are electrically connected to the projection (6) through the constricted portion (9) of the hole (4) which is filled with an electrically and heat conducting material (11). The wide section (10) of the hole (4) is from 0.2.times.0.2 mm to the size of the chip (7), and the distance between the side walls of the projection (6) and the side walls of the wide section (10) of the hole (4) is 0.001 to 1.0 mm.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: December 14, 1999
    Assignee: Samsung Electronics Company
    Inventors: Viktor Anatolievich Iovdalsky, Eduard Volfovich Aizenberg, Vladimir Iliich Beil, Mikhail Ivanovich Lopin
  • Patent number: 5917227
    Abstract: A light-emitting-diode array includes a non-doped compound semiconductor layer between a substrate and a first compound semiconductor layer. A plurality of isolation regions extend from the first compound semiconductor layer to the surface of the non-doped compound semiconductor layer, and provide separation into isolated block regions each containing an equal number of diffusion regions. A plurality of shared electrode lines are connected to the diffusion regions in a plurality of the block regions, in such a relationship that diffusion regions selected from each of the block regions are connected to a common shared electrode. At least a surface portion of the substrate is formed of silicon. The density of the diffusion regions can be increased without increasing the number of the electrode pads. Moreover, the substrate is free from breakage or cracks.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: June 29, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuhiko Ogihara, Yukio Nakamura, Masumi Taninaka, Hiroshi Hamano
  • Patent number: 5612556
    Abstract: A monolithic integrated circuit capable of operation in the microwave range which is fabricated using silicon technology wherein transmission line interconnects are fabricated along with active devices on the same substrate. The transmission line is provided using polycrystalline silicon since it can have much higher resistivity than single crystal silicon. Accordingly, a circuit is provided wherein active devices are provided in single crystal silicon and interconnects are formed overlying polycrystalline silicon to provide transmission line interconnects between devices and obtain the desired high frequency response.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: March 18, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Satwinder Malhi, Chi-Cheong Shen, Oh-Kyong Kwon
  • Patent number: 5559359
    Abstract: A passive element structure and method for a microwave integrated circuit reduces signal propagation losses. In one approach, a passive element (10) has an insulating layer (12) overlying a silicon substrate (14). A metal layer (16) comprising a signal line (18) and a groundplane (20) is disposed overlying the insulating layer (12), and at least a portion of the metal layer (16) contacts the substrate (14) through at least one opening (22, 24) in the insulating layer (12). The silicon substrate (14) has a resistivity greater than 2,000 ohm-cm, and the passive element (10) preferably carries signals having frequencies greater than 500 MHz. Signal losses in the passive element (10) are minimized because the charge density at the surface (15) of the substrate (14) underlying the metal layer (16) is significantly reduced. In one example, the passive element (10) is a coplanar waveguide transmission line.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: September 24, 1996
    Inventor: Adolfo C. Reyes
  • Patent number: 5488253
    Abstract: A semiconductor device includes a semiconductor substrate having opposite front and rear surfaces; lower electrodes disposed on the front surface of the substrate and a rear electrode disposed on the rear surface of the substrate; an air-bridge wiring disposed on the front surface of the substrate and connecting two of the lower electrodes; a via-hole penetrating through the semiconductor substrate in the vicinity of the two selected lower electrodes; and via-hole wiring disposed in the via-hole and connecting the selected lower electrodes to the rear electrode, the air-bridge wiring and the via-hole wiring being a continuous, unitary electroplated metal film. The air-bridge wiring and the via-hole wiring are directly connected without any intermediate wiring so that a junction of these wirings has no contact resistance. Further, since these wirings are continuous in the electroplated metal film, mechanical strength and reliability are improved.
    Type: Grant
    Filed: November 4, 1994
    Date of Patent: January 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Matsuoka
  • Patent number: 5371400
    Abstract: Desirably, a Schottky barrier semiconductor diode has low forward direction rising voltage and high inverse direction yield voltage. A semiconductor device is provided with a first metal producing a low Schottky barrier and a second metal producing a high Schottky barrier. The forward direction rising voltage is reduced on account of the first metal. The inverse direction yield voltage, which is decreased due to the lowered forward rising voltage, is compensated for upon linking of depletion regions generated by forming the PN junction under the first metal layer and not under the second metal layer. As a result, a high inverse yield voltage is realized.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: December 6, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Keiji Sakurai
  • Patent number: 5347149
    Abstract: Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.
    Type: Grant
    Filed: November 29, 1989
    Date of Patent: September 13, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 5343065
    Abstract: The hold current of a breakover type surge protection device is increased by irradiating the device with .gamma. or x rays so as to form crystal lattice defects in the semiconductor regions thereof.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: August 30, 1994
    Assignee: Sankosha Corporation
    Inventor: Takashi Saitou
  • Patent number: 5278444
    Abstract: A planar frequency tripler comprised of two semiconductor diode structures connected back-to-back by an n.sup.+ doped layer (N.sup.+) of semiconductor material utilizes an n doped semiconductor material for a drift region (N) over the back contact layer in order to overcome a space charge limitation in the drift region. A barrier layer (B) is grown over the drift region, after a sheet of n-type doping (N.sub.sheet) which forms a positive charge over the drift region, N, to internally bias the diode structure. Two metal contacts are deposited over the barrier layer, B, with a gap between them. To increase the power output of the diodes of a given size, stacked diodes may be provided by alternating barrier layers and drift region layers, starting with a barrier layer and providing a positive charge sheet at the interface of a barrier on both sides of each drift region layer with n-type .delta. doping. The stacked diodes may be isolated by etching or ion implantation to the back contact layer N.sup.
    Type: Grant
    Filed: February 26, 1992
    Date of Patent: January 11, 1994
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Udo Lieneweg, Margaret A. Frerking, Joseph Maserjian