Avalanche Diode (e.g., So-called "zener" Diode Having Breakdown Voltage Greater Than 6 Volts) Patents (Class 257/481)
  • Patent number: 10665727
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having a top surface, a first well region of a first conductivity type in the semiconductor substrate, a second well region of a second conductivity type in the semiconductor substrate, laterally surrounding the first well region, and an isolation region in the first well region and the second well region in proximity to the top surface. The first well region includes a first lighter doped region in proximity to the top surface, and a heavier doped region under the first lighter doped region. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
  • Patent number: 10658456
    Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10658523
    Abstract: The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p+-type anode layer disposed to include a position right under a portion where the wire is connected; and a p?-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p+-type anode layer is higher than an impurity concentration of the p?-type anode layer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeto Honda, Fumihito Masuoka, Yuki Haraguchi
  • Patent number: 9899541
    Abstract: Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hyun Yoo
  • Patent number: 9466735
    Abstract: A junction barrier Schottky diode is formed by shifting second semiconductor regions of a second conductivity type in a staggered shape in a first semiconductor region of a first conductivity type so that pn junction regions are formed at predetermined distances between the second semiconductor regions and the first semiconductor region. A third semiconductor region of the first conductivity type is formed between the second semiconductor regions in order to form a Schottky junction region. An electrode is formed on the second and third semiconductor regions. The second semiconductor regions arranged at equal distances in an X direction are formed in a plurality of columns in a Y direction. An amount of shift between adjacent columns in the X direction is set such that a Y-direct ion distance between the second semiconductor regions in the different columns is larger than an X-direction distance between the second semiconductor regions in each column.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: October 11, 2016
    Assignee: Synaptics Display Devices GK
    Inventor: Tomoaki Tanaka
  • Patent number: 9391197
    Abstract: A semiconductor device includes a substrate; a deep well region disposed in the substrate; an element region disposed in the substrate and in the deep well region; a drain region disposed in the substrate, in the deep well region, and surrounding the element region; a gate structure disposed on the surface of the substrate, adjacent to the deep well region, and surrounding the drain region; a well region disposed in the substrate, in the deep well region, and surrounding the gate structure; a source region disposed in the substrate, in the well region, and surrounding the gate structure; a body contact region disposed separately from the source region in the well region and surrounding the source region; and an annular doped region disposed separately from the deep well region in the substrate and surrounding the deep well region.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shih Chieh Pu, Ming-Tsung Lee, Cheng-Hua Yang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9200953
    Abstract: A spectrometer including: a photodiode having a depleted region and generating an electrical detection signal indicating instants of detection of optical pulses; a converter generating an electrical delay signal, indicating delays between the instants of detection and corresponding instants of emission of the optical pulses; a memory, storing a theoretical function corresponding to the probability of triggering an avalanche by a charge carrier generated in the depleted region; and a computing stage which determines a statistical distribution of the delays between the instants of detection and the corresponding instants of emission; selects a Gaussian portion of the statistical distribution; calculates the ratio between the sum of the number of delays of the Gaussian portion and the sum of the number of delays of the statistical distribution; and determines an estimate of the wavelength of the optical pulses on the basis of the theoretical function and of the sample value.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 1, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 9000551
    Abstract: A GeSi avalanche photodiode (APD includes an anti-reflection structure, a Ge absorption region, and a resonance cavity enhanced (RCE) reflector. The anti-reflection structure includes one or more dielectric layers and a top contact layer which is heavily doped with dopants of a first polarity. The RCE reflector includes: an intrinsic or lightly doped Si multiplication layer, a Si contact layer which is heavily doped with dopants of a second polarity opposite the first polarity, a Si cavity length compensation layer, a buried oxide (BOX) layer, and a Si substrate.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 7, 2015
    Assignee: SiFotonics Technologies Co, Ltd.
    Inventors: Mengyuan Huang, Tuo Shi, Pengfei Cai, Dong Pan
  • Patent number: 9000481
    Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: April 7, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Jun Hu, Wayne F. Eng
  • Patent number: 8981476
    Abstract: A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazuhiko Takada
  • Patent number: 8981517
    Abstract: A solid-state image pickup element 1 is structured so as to include: a semiconductor layer 2 having a photodiode formed therein, photoelectric conversion being carried out in the photodiode; a first film 21 having negative fixed charges and formed on the semiconductor layer 2 in a region in which at least the photodiode is formed; and a second film 22 having the negative fixed charges, made of a material different from that of the first film 21 having the negative fixed charges, and formed on the first film 21 having the negative fixed charges.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Itaru Oshiyama, Susumu Hiyama
  • Patent number: 8975661
    Abstract: An asymmetrical bidirectional protection component formed in a semiconductor substrate of a first conductivity type, including: a first implanted area of the first conductivity type; a first epitaxial layer of the second conductivity type on the substrate and the first implanted area; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the second layer having a doping level different from that of the first layer; a second area of the first conductivity type on the outer surface of the epitaxial layer, opposite to the first area; a first metallization covering the entire lower surface of the substrate; and a second metallization covering the second area.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Benjamin Morillon
  • Patent number: 8963252
    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a semiconductor element disposed on a substrate and including an insulating layer and a gate electrode, a doped region having a first conductivity-type on the substrate, a conductive interconnection electrically connected to the gate electrode, and a first contact plug having a second conductivity-type and electrically connecting the conductive interconnection and the doped region to each other and constituting a Zener diode by junction with the doped region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moojin Kim, Jeongyun Lee
  • Patent number: 8890277
    Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: November 18, 2014
    Assignee: University of Florida Research Foundation Inc.
    Inventors: Arthur Foster Hebard, Sefaattin Tongay
  • Patent number: 8878276
    Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 8836066
    Abstract: An avalanche photodiode includes silicon crystal doped with impurities, where the doping profile of the silicon crystal includes a smoothly arcing donor-acceptor concentration curve decreasing with respect to distance into the interior of the silicon crystal that is interrupted by a narrower peak of increased concentration in the interior of the silicon crystal prior to further decreasing with respect to distance along the smoothly arcing donor-acceptor concentration curve.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 16, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Robert G. Brown, Steven E. Koenck
  • Patent number: 8791547
    Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: July 29, 2014
    Assignee: Infineon Technologies AG
    Inventors: Jens Schneider, Kai Esmark, Martin Wendel
  • Patent number: 8742534
    Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 3, 2014
    Assignee: DENSO CORPORATION
    Inventors: Takao Yamamoto, Norihito Tokura, Hisato Kato, Akio Nakagawa
  • Patent number: 8729605
    Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: May 20, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8698196
    Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 15, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Jun Hu, Wayne F. Eng
  • Patent number: 8592863
    Abstract: A photodetector with internal gain comprising a semiconductor structure in which impact ionization events are produced mostly by minority charge carriers; a first biasing contact and a second biasing contact located in the semiconductor structure; a means of defining, in the semiconductor structure, a photon collection region close to first biasing contact; a P-N type junction formed in the semiconductor structure between the two biasing contacts and close to the second biasing contact; and a collector contact which is located in the P-N junction and used to collect current in the P-N junction.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 26, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Johan Rothman, Jean-Paul Chamonal
  • Patent number: 8575695
    Abstract: This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 5, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Anup Bhalla, Hamza Yilmaz, Wilson Ma, Lingpeng Guan, Yeeheng Lee, John Chen
  • Publication number: 20130207222
    Abstract: A semiconductor chip, which includes an n-type substrate, over which an n-type epitaxial layer having trenches introduced into the epitaxial layer and filled with p-type semiconductor is situated, the trenches each having a heavily doped p-type region on their upper side, the n+-type substrate being situated in such a manner, that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present; a first metallic layer, which is provided on the front side of the semiconductor chip, forms an ohmic contact with the heavily doped p-type regions and is used as an anode electrode; a second metallic layer, which is provided on the back side of the semiconductor chip, constitutes an ohmic contact and is used as a cathode electrode; a dielectric layer provided, in each instance, between an n-type region and an adjacent p-type region, as well as p-type layers provided between the n-type regions and the first metallic layer.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 15, 2013
    Applicant: Robert Bosch GmbH
    Inventors: Ning QU, Alfred GOERLACH
  • Patent number: 8508052
    Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: August 13, 2013
    Assignee: Intersil Americas Inc.
    Inventors: David B. Bell, Francois Hebert, Nikhil Kelkar
  • Patent number: 8497563
    Abstract: A semiconductor system having a trench MOS barrier Schottky diode, having an integrated substrate PN diode as a clamping element (TMBS-ub-PN), suitable in particular as a Zener diode having a breakdown voltage of approximately 20V for use in a vehicle generator system, the TMBS-sub-PN being made up of a combination of Schottky diode, MOS structure, and substrate PN diode, and the breakdown voltage of substrate PN diode BV_pn being lower than the breakdown voltage of Schottky diode BV_schottky and the breakdown voltage of MOS structure BV_mos.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: July 30, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8492866
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Patent number: 8471293
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Patent number: 8445917
    Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: May 21, 2013
    Assignee: Cree, Inc.
    Inventors: Sarah Kay Haney, Sei-Hyung Ryu
  • Patent number: 8399894
    Abstract: A wiring electrode is provided on a mount substrate. A light emitting element is provided on the wiring electrode to connect electrically with the wiring electrode and is configured to emit a blue to ultraviolet light. A reflective film is provided above the light emitting element to cover the light emitting element so that a space is interposed between the reflective film and the light emitting element. The reflective film is capable of transmitting the blue to ultraviolet light. A fluorescent material layer is provided above the light emitting element to cover the light emitting element so that the reflective film is located between the fluorescent material layer and the light emitting element. A light from the fluorescent material layer is reflected by the reflective film.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Furuyama
  • Patent number: 8368145
    Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Patent number: 8339758
    Abstract: A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Mingjiao Liu, Ali Salih, Emmanuel Saucedo-Flores, Suem Ping Loo
  • Publication number: 20120256192
    Abstract: An electronic device includes a drift region, a Schottky contact on a surface of the drift region, and an edge termination structure in the drift region adjacent the Schottky contact. The edge termination structure includes a recessed region that is recessed from the surface of the drift region by a distance d that may be about 0.5 microns.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Inventors: Qingchun Zhang, Jason Henning
  • Patent number: 8227855
    Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: July 24, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph Yedinak, Mark Rinehimer, Thomas E. Grebs, John Benjamin
  • Patent number: 8217419
    Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 10, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8212327
    Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 3, 2012
    Assignee: SiOnyx, Inc.
    Inventors: Neal T. Kurfiss, James E. Carey, Xia Li
  • Patent number: 8212281
    Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: July 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 8198703
    Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: June 12, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8188563
    Abstract: Techniques and apparatus for using single photon avalanche diode (SPAD) devices in various applications.
    Type: Grant
    Filed: July 21, 2007
    Date of Patent: May 29, 2012
    Assignee: The Regents of the University of California
    Inventors: Hod Finkelstein, Sadik C. Esener
  • Patent number: 8159039
    Abstract: A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: April 17, 2012
    Assignee: Icemos Technology Ltd.
    Inventor: Xu Cheng
  • Patent number: 8125008
    Abstract: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 28, 2012
    Assignee: System General Corporation
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin
  • Patent number: 8124981
    Abstract: A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: February 28, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher L. Rexer, Gary M. Dolny, Richard L. Woodin, Carl Anthony Witt, Joseph Shovlin
  • Patent number: 8093133
    Abstract: Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Emmanuel Saucedo-Flores, Mingjiao Liu, Francine Y. Robb, Ali Salih
  • Patent number: 8044486
    Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 25, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: François Hébert
  • Patent number: 8044520
    Abstract: A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Masaki Shiraishi, Tetsuya Kawashima, Koji Tateno, Nobuyoshi Matsuura
  • Patent number: 8035195
    Abstract: A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor layer and the metallization. The contact area includes at least one first semiconductor area that has a second doping density higher than the first doping density, and at least one second semiconductor area in the semiconductor layer. The second semiconductor area is in contact with the metallization and provides lower ohmic resistance to the metallization than a direct contact between the semiconductor layer and the metallization provides or would provide.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 11, 2011
    Assignee: Infineon Technologies AG
    Inventors: Franz Josef Niedernostheide, Manfred Pfaffenlehner, Hans-Joachim Schulze
  • Patent number: 7982277
    Abstract: A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator wafer (UTSOI) is disclosed. The UTSOI wafer includes a mechanical substrate, an insulator layer, and a seed layer. At least one dopant is applied to the semiconductor substrate. A first portion of an epitaxial layer is grown on the seed layer. A predefined concentration of carbon impurities is introduced into the first portion of the epitaxial layer. A remaining portion of the epitaxial layer is grown. During the epitaxial growth process, the at least one dopant diffuses into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile which has an initial maximum value at an interface between the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within at least a portion of at least one of the semiconductor substrate and the epitaxial layer.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: July 19, 2011
    Assignee: SRI International
    Inventor: Lawrence Alan Goodman
  • Patent number: 7928533
    Abstract: An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: April 19, 2011
    Assignee: California Institute of Technology
    Inventors: Xinyu Zheng, Bedabrata Pain, Thomas J. Cunningham
  • Patent number: 7919790
    Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.
    Type: Grant
    Filed: February 8, 2009
    Date of Patent: April 5, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Michio Nemoto
  • Patent number: 7902570
    Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: March 8, 2011
    Assignee: Princeton Lightwave, Inc.
    Inventors: Mark Allen Itzler, Rafael Ben-Michael, Sabbir Sajjad Rangwala
  • Patent number: 7893464
    Abstract: A method of manufacture of an avalanche photodiode involving a step of making a recess in a top window layer of an avalanche photodiode layer stack, such that a wall surrounding the recess runs smoothly and gradually from the level of the recess to the level of the window layer. Further, diffusing a dopant over the entire window layer area so as to form a p-n junction at the bottom of the recess, and providing a first electrical isolation region around the recess by buried ion implantation or wet oxidation in order to limit the flow of electrical current to the p-n junction. Forming an isolation trench around the photodiode and a second electrical isolation region by ion implantation into the trench such that the second electrical isolation region runs through the absorption layer of the photodiode.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 22, 2011
    Assignee: JDS Uniphase Corporation
    Inventors: Syn-Yem Hu, Zhong Pan