Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.

Abstract: Group III-V composites, which is used to manufacture Schottky contacts having the characteristics of higher energy gap, higher carriers mobility, etc., are applied for manufacturing high-speed devices. Therefore, in there years, Group III-V composite Schottky contacts are continuously being developed. In the invention, the surface treatment of composite semiconductor is used for reduce a surface state and oxidation, thereby increased the Schottky barriers of the Group III-V composite (such as, GaAs, InP, InAs and InSb) Schottky contacts. During experiments, a phosphorus sulphide/ammonia sulphide solution and hydrogen fluoride solution are used for the surface treatment to increase the amount of sulphur contained on the surfaces of substrates, reduce the surface state and remove various oxides. Furthermore, ultra-thin and really stable sulphur fluoride/phosphorus fluoride layers having high energy gaps are formed on various substrates.

Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.

Abstract: In an HEMT, a channel forming layer is arranged above a semi-insulating substrate via a buffer layer. A spacer layer is arranged on the channel forming layer and an electron supplying layer and a Schottky contact layer are sequentially arranged on the spacer layer. A diffusion preventing layer, for preventing a metal element of a gate electrode from diffusing into the channel forming layer, is arranged in the Schottky contact layer.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A semiconductor device having a Schottky gate and a bipolar device. A semiconductor substrate has a surface layer in ohmic contact with the conductor and the deeper layer in Schottky contact with the conductor. The substrate has a recess which reaches into the deeper layer. A conductor field extends from the bottom of the recess in a direction perpendicular to the bottom. Insulating films are formed on both vertical surfaces of the conductor film. Another conductor film is formed across the top of the first conductor film and both insulating films. Conductor films are formed on the surface of the substrate on either side of the insulating films. In this device, the electrode length/width is reduced and the response to the element is improved. Further, because the second conductor film is formed on the first conductor film, it is possible to reduce the gate electrode and the base electrode.

Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.

Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

Abstract: A semiconductor device structure having a semiconductor device on a substrate with a layer of benzocyclobutane (BCB) disposed about the device with a via between the top surface of the BCB and the device is disclosed. A bond pad is in contact with the via and is connected to a bond ribbon.

Abstract: An optoelectronic component has an Al.sub.2 O.sub.3 or Si substrate having a surface on which a buried CoSi.sub.2 layer is provided, a Si layer overlying the buried CoSi.sub.2 layer. A metal layer on a portion of this latter Si layer forms a diode between the metal layer, the underlying portion of the Si layer and the buried CoSi.sub.2 layer and a waveguide for a transparent portion of the metal layer delivers photon energy to the underlying portion of the Si layer.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order.

Abstract: A semiconductor device comprising an electrode formed on a semiconductor diamond. The electrode includes a first metal section which is in contact with a surface of the semiconductor diamond and which has a thickness of 100 nm or smaller, and further including a second metal section which is in contact with the first metal section and which has a thickness of equal to or larger than four times the thickness of the first metal section. The second metal section is made of a metal having a melting point of 1000.degree. C. or higher.

Abstract: A semiconductor photo detector has its construction such that on a substrate made of InP are formed light absorption layer having a supperlattice structure made of n- type InGaAsP and InAsP, an intermediate layer made of n- type InGaAs, a multiplication layer made of n- type InP and a layer made of p- type layer. The light having a wavelength 1.65 .mu.m being made incident into the detector from the p- type InP layer is absorbed in the superlattice structure light absorption layer of n- type InGaAs/InAsP and changed into carriers, which flowed out an external circuit. Since the superlattice of InGaAs and InAsP makes a lattice matching to InP, it may be possible to prevent that a dark current is generated by a lattice mismatching. The carriers generated by the absorbed light in the light absorption layer pass from the p type side electrode 11 into an external circuit via the n type InGaAsP intermediate layer 4, n+ type InP multiplication layer 5 and p+ type InP layer 8.

Abstract: An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Abstract: A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) over one portion of a substrate, while leaving portions the polysilicon layer (31, 33, 29) intact over other portions of the substrate (22b). Multi-layer metal electrodes are deposited and patterned to form a rectifying schottky contact to the exposed single crystal region (22a), and to form an ohmic contact to the exposed polysilicon (31, 33, 29).

Abstract: A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

Abstract: A sensing transducer (10,30) and a method therefor uses a Schottky junction (12) having a conductive layer (16) disposed on a semiconductor substrate (14). The conductive layer (16) is generally formed from the reaction of a metal with a portion of the semiconductor substrate (14). One example of the conductive layer (16) is a metal silicide layer. In one pressure sensing approach, a substantially constant reverse current (I.sub.1) is applied to the Schottky junction (12). The change in reverse output voltage of the junction (12) is proportional to the change in pressure on the junction (12) itself, and can thus be used to sense pressure. This output voltage change is significantly higher than that achieved with prior pressure transducers and permits the output signal of the transducer (10,30) according to the present invention to be substantially used without extra amplification or other conditioning.

Abstract: A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs.

Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Abstract: Gold, which is the commonly used metallization on .beta.-silicon carbide, is known to degrade at temperatures above 450.degree. C. It also exhibits poor adhesion to silicon carbide. Schottky contacts with platinum metallization have rectifying characteristics similar to contacts with gold metallization. The platinum Schottky contacts remain stable up to 800.degree. C. Adhesion of the platinum deposited at slightly elevated temperatures is also superior to that for gold. Platinum provides a metallization that is physically more rugged and thermally more stable than conventional gold metallization.

Abstract: Epitaxial growth of films on single crystal substrates having a lattice mismatch of at least 10% through domain matching is achieved by maintaining na.sub.1 within 5% of ma.sub.2, wherein a.sub.1 is the lattice constant of the substrate, a.sub.2 is the lattice constant of the epitaxial layer and n and m are integers. The epitaxial layer can be TiN and the substrate can be Si or GaAs. For instance, epitaxial TiN films having low resistivity can be provided on (100) silicon and (100) GaAs substrates using a pulsed laser deposition method. The TiN films were characterized using X-ray diffraction (XRD), Rutherford back scattering (RBS), four-point-probe ac resistivity, high resolution transmission electron microscopy (TEM) and scanning electron microscopy (SEM) techniques. Epitaxial relationship was found to be <100> TiN aligned with <100> Si. TiN films showed 10-20% channeling yield. In the plane, four unit cells of TiN match with three unit cells of silicon with less than 4.0% misfit.

Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is (111) is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

Abstract: In accordance with the present invention, a silicon device fabricated on a (100) silicon substrate is provided with a (111) slant surface and an electrical contact comprising epitaxial low Schottky barrier silicide is formed on the (111) surface. For example, low resistance rare earth silicide contacts on V-groove surfaces are provided for the source and drain contacts of a field effect transistor. The resulting high quality contact permits downward scaling of the source and drain junction depths. As another example, rare earth silicide Schottky contacts are epitaxially grown on V-groove surfaces to provide low voltage rectifiers having both low power dissipation under forward bias and low reverse-bias leakage current.

Abstract: A planar frequency tripler comprised of two semiconductor diode structures connected back-to-back by an n.sup.+ doped layer (N.sup.+) of semiconductor material utilizes an n doped semiconductor material for a drift region (N) over the back contact layer in order to overcome a space charge limitation in the drift region. A barrier layer (B) is grown over the drift region, after a sheet of n-type doping (N.sub.sheet) which forms a positive charge over the drift region, N, to internally bias the diode structure. Two metal contacts are deposited over the barrier layer, B, with a gap between them. To increase the power output of the diodes of a given size, stacked diodes may be provided by alternating barrier layers and drift region layers, starting with a barrier layer and providing a positive charge sheet at the interface of a barrier on both sides of each drift region layer with n-type .delta. doping. The stacked diodes may be isolated by etching or ion implantation to the back contact layer N.sup.

Abstract: A thin-film ROM device includes an array of open circuit and closed-circuit cells (5 to 8) formed from a stack of thin films (12,21,22,23,11) on a glass or other substrate (10). The semiconductor films (21,22,23) may be of hydrogenated amorphous silicon. At least one of the semiconductor films (21,22,23) is removed from some of the closed-circuit cell areas (5,7,8) before depositing the next film. In this way, at least a second type of thin-film diode (MIM, MIN, MIP) is formed having a different conduction characteristic to that of a first type (NIP), so increasing the information content of the ROM array. A lower semiconductor film (23) can be readily etched away from the lower electrode film (11) by a selective etching treatment in which the electrode film (11) acts as an etch stop. By monitoring emissions during plasma etching, an upper semiconductor film (21 or 22) can be removed from a lower semiconductor film (22 or 23).

Abstract: An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.

Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.

Abstract: A semiconductor device having a reliable contact is disclosed. The device includes a barrier film deposited on the bottom and side wall of a contact hole opened in a insulating film at a predetermined position; a first metal film filled in the contact hole; and a second metal film of low resistance for forming an interconnection which passes above the contact hole filled in with the first metal film. An oxide film is formed by oxidation on the barrier metal film. And a method of manufacturing the semiconductor device is disclosed.

Abstract: Schottky barrier diode comprises a Schottky contact layer having an increased periphery to area ratio. In the illustrated embodiment, the Schottky contact layer comprises a plurality of individual contact regions interconnected by an overlying metallization layer.