Specified Materials Patents (Class 257/485)
  • Patent number: 9847420
    Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventor: Pushkar Ranade
  • Patent number: 9755039
    Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsueh Wen Tsau
  • Patent number: 9282638
    Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: March 8, 2016
    Assignee: ZYCUBE CO., LTD.
    Inventors: Manabu Bonkohara, Hirofumi Nakamura, Qiwei He
  • Patent number: 9093529
    Abstract: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 28, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hidenobu Fukutome, Tomohiro Kubo
  • Patent number: 9006858
    Abstract: In a Schottky diode having an n+-type substrate, an n-type epitaxial layer, at least two p-doped trenches introduced into the n-type epitaxial layer, mesa regions between adjacent trenches, a metal layer functioning as a cathode electrode, and another metal layer functioning as an anode electrode, the thickness of the epitaxial layer is more than four times the depth of the trenches.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 14, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8933531
    Abstract: A semiconductor device including a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) generated within the semiconductor layer; a plurality of first ohmic electrodes which are disposed on the central region of the semiconductor layer and have island-shaped cross sections; a second ohmic electrode which is disposed on edge regions of the semiconductor layer; and a Schottky electrode part has first bonding portions bonded to the first ohmic electrodes, and a second bonding portion bonded to the semiconductor layer. A depletion region is provided to be spaced apart from the 2DEG when the semiconductor device is driven at an on-voltage and is provided to be expanded to the 2DEG when the semiconductor device is driven at an off-voltage, the depletion region being generated within the semiconductor layer by bonding the semiconductor layer and the second bonding portion.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Cul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Patent number: 8901699
    Abstract: Integral structures that block the current conduction of the built-in PiN diode in a junction barrier Schottky (JBS) structure are provided. A Schottky diode may be incorporated in series with the PiN diode, where the Schottky diode is of opposite direction to that of the PiN diode. A series resistance or and insulating layer may be provided between the PiN diode and a Schottky contact. Silicon carbide Schottky diodes and methods of fabricating silicon carbide Schottky diodes that include a silicon carbide junction barrier region disposed within a drift region of the diode are also provided. The junction barrier region includes a first region of silicon carbide having a first doping concentration in the drift region of the diode and a second region of silicon carbide in the drift region and disposed between the first region of silicon carbide and a Schottky contact of the Schottky diode. The second region is in contact with the first region of silicon carbide and the Schottky contact.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: December 2, 2014
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal
  • Publication number: 20140306315
    Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).
    Type: Application
    Filed: June 25, 2014
    Publication date: October 16, 2014
    Applicant: THE UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE
    Inventors: Raphael TSU, Wattaka SITAPURA, John HUDAK
  • Patent number: 8836071
    Abstract: A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: September 16, 2014
    Assignee: Avogy, Inc.
    Inventors: Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, Madhan Raj
  • Patent number: 8830725
    Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Donald S Bethune, Kailash Gopalakrishnan, Andrew J Kellock, Rohit S Shenoy, Kumar R Virwani
  • Patent number: 8823148
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substra
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Takashi Shinohe, Makoto Mizukami, Johji Nishio
  • Patent number: 8809988
    Abstract: A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: August 19, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ji-Hyoung Yoo, Martin E. Garnett
  • Patent number: 8610233
    Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 8476731
    Abstract: In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: July 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Takashi Ishigaki
  • Patent number: 8436365
    Abstract: A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: May 7, 2013
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Jun Morimoto, Hirokazu Fujiwara, Yukihiko Watanabe, Takashi Katsuno, Tsuyoshi Ishikawa
  • Patent number: 8426939
    Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 23, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Patent number: 8384182
    Abstract: A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: February 26, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Michael S. Mazzola, Lin Cheng
  • Patent number: 8373245
    Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: February 12, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Patent number: 8368168
    Abstract: A III-V-group compound semiconductor device includes a substrate, a channel layer provided over the substrate, a barrier layer provided on the channel layer so as to form a hetero-interface, a plurality of electrodes provided on the barrier layer, an insulator layer provided to cover an entire upper surface of the barrier layer except for at least partial regions of the electrodes, and a hydrogen-absorbing layer stacked on the insulator layer or an integrated layer in which an hydrogen-absorbing layer is integrated with the insulator layer.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: February 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kunihiro Takatani
  • Patent number: 8362585
    Abstract: A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: January 29, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Anup Bhalla, Ji Pan, Daniel Ng
  • Patent number: 8343864
    Abstract: A semiconductor circuit and method of fabrication is disclosed. In one embodiment, the semiconductor circuit comprises a metal-insulator-metal trench capacitor in a silicon substrate. A field effect transistor is disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor, and a silicide region is disposed between the field effect transistor and the metal-insulator-metal trench capacitor. Electrical connectivity between the transistor and capacitor is achieved without the need for a buried strap.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Puneet Goyal, Herbert Lei Ho, Pradeep Jana, Jin Liu
  • Patent number: 8319309
    Abstract: The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: November 27, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Patent number: 8274076
    Abstract: A diode includes an organic composite plate, a first electrode and a second electrode. The organic composite plate includes a first portion, a second portion and a plurality of carbon nanotubes distributed therein. The carbon nanotubes in the first portion have a first band gap and the carbon nanotubes in the second portion have a second band gap. The first band gap and the second band gap are different from each other. The first electrode is electrically connected to the first portion. The second electrode electrically is connected to the second portion.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 25, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Chun-Hua Hu, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 8227811
    Abstract: A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a <11-20> direction of the layer.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Johji Nishio
  • Patent number: 8178864
    Abstract: A diode having a reference voltage electrode, a variable voltage electrode, and a diode material between the electrodes. The diode material is formed of at least one high-K dielectric material and has an asymmetric energy barrier between the reference voltage electrode and the variable voltage electrode, with the energy barrier having a relatively maximum energy barrier level proximate the reference voltage electrode and a minimum energy barrier level proximate the variable voltage electrode.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 15, 2012
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Wei Tian, Venugopalan Vaithyanathan, Cedric Bedoya, Markus Siegert
  • Patent number: 8178940
    Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 15, 2012
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
  • Patent number: 8169079
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer and a barrier layer including a metal element and copper, formed between the insulating layer and the interconnection body. An atomic concentration of the metal element in the barrier layer is accumulated toward an outer surface of the barrier layer facing the insulating layer, and an atomic concentration of copper in the barrier layer is accumulated toward an inner surface of the barrier layer facing the interconnection body. The inner surface of the barrier layer comprises copper surface orientation of {111} and {200}, and an intensity of X-ray diffraction peak from the inner surface of the barrier layer is stronger for the {111} peak than for the {200} peak.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: May 1, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 8154025
    Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: April 10, 2012
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 8039919
    Abstract: In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Ho Moon, Hong-Sik Yoon, Subramanya Mayya, Sun-Woo Lee, Dong-Woo Kim, Xiaofeng Wang
  • Patent number: 8022482
    Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: September 20, 2011
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Yongzhong Hu, Sung-Shan Tai
  • Publication number: 20110221027
    Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode (301,303) and an alloy electrode (502,602). The device also includes an active region (510,610) sandwiched between the electrode and the alloy electrode. The alloy electrode forms dopants in a sub-region of the active region adjacent to the alloy electrode. The active region can be operated by selectively positioning the dopants within the active region to control the flow of charge carriers between the electrode and the alloy electrode.
    Type: Application
    Filed: January 26, 2009
    Publication date: September 15, 2011
    Inventors: Nathaniel J. Quitoriano, Douglas Ohlberg, Philip J. Kuekes, Jianhua Yang
  • Patent number: 8018021
    Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Shik Kim, Oh-Kyum Kwon, Myung-Hee Kim, Yong-Chan Kim, Hye-Young Park, Joon-Suk Oh
  • Patent number: 7994602
    Abstract: A thin-film metal-oxide compound includes a titanium dioxide layer having a thickness of about 100 to 1000 nanometers. The titanium dioxide layer has a single-phase anatase structure. The titanium dioxide layer is directly disposed on a substrate comprised of glass, sapphire, or silicon. A solar cell includes a backing layer, a p-n junction layer, a metal-oxide layer, a top electrical layer and a contact layer. The backing layer includes a p-type semiconductor material. The p-n junction layer has a first side disposed on a front side of the backing layer. The metal-oxide layer includes an n-type titanium dioxide film having a thickness in the range of about 100 to about 1000 nanometers. The metal-oxide layer is disposed on a second side of the p-n junction layer. The top electrical layer is disposed on the metal-oxide layer, and the contact layer is disposed on a back side of the backing layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: August 9, 2011
    Assignee: Wayne State University
    Inventors: Ibrahim Abdullah Al-Homoudi, Golam Newaz, Gregory W. Auner
  • Patent number: 7985615
    Abstract: The present invention relates to embodiments of TPV cell structures based on carbon nanotube and nanowire materials. One embodiment according to the present invention is a p-n junction carbon nanotube/nanowire TPV cell, which is formed by p-n junction wires. A second embodiment according to the present invention is a carbon nanotube/nanowire used as a p-type (or n-type), and using bulk material as the other complementary type to a form p-n junction TPV cell. A third embodiment according to the present invention uses a controllable Schottky barrier height between a one-dimensional nanowire and a metal contact to form the built-in potential of the TPV cells.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 26, 2011
    Assignee: The Regents of the University of California
    Inventors: Fei Liu, Ma Siguang, Kang L. Wang
  • Publication number: 20110156199
    Abstract: A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.
    Type: Application
    Filed: September 3, 2009
    Publication date: June 30, 2011
    Applicant: Monolithic Power Systems, Incc
    Inventors: Ji-Hyoung Yoo, Martin E. Garnett
  • Patent number: 7829970
    Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: November 9, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Dev Alok Girdhar, Michael David Church
  • Publication number: 20100258897
    Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
    Type: Application
    Filed: June 14, 2010
    Publication date: October 14, 2010
    Inventors: Sik K. Lui, Anup Bhalla
  • Patent number: 7777292
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Johji Nishio, Tetsuo Hatakeyama, Takashi Shinohe
  • Patent number: 7768016
    Abstract: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell including a resistivity changing memory element and a carbon diode electrically coupled to the resistivity changing memory element.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: August 3, 2010
    Assignee: Qimonda AG
    Inventor: Franz Kreupl
  • Patent number: 7759678
    Abstract: A diode includes an organic composite plate, a pressing element, a first electrode, and a second electrode. The organic composite plate has a plurality of carbon nanotubes uniformly distributed therein and includes a first portion and a second portion opposite to the first portion. The pressing element is disposed on the first portion of the organic composite plate. The first and second electrodes are electrically connected to the first and second portions of the organic composite plate, respectively. The diode employed with the carbon nanotubes has a changeable characteristic, such as voltage, current, via controlling the pressure applied by the pressing element.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 20, 2010
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Chun-Hua Hu, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 7755104
    Abstract: A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the curre
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Yagishita
  • Patent number: 7750426
    Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: July 6, 2010
    Assignee: Intersil Americas, Inc.
    Inventors: Dev Alok Girdhar, Michael David Church, Alexander Kalnitsky
  • Patent number: 7749877
    Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and an ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form and SiO2 passivation layer to improve the self aligned process.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Siliconix Technology C. V.
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 7701031
    Abstract: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is disposed above the lightly doped region. The Schottky contact metal layer and the substrate form a Schottky diode. The material of the contact window is different from that of the Schottky contact metal layer.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: April 20, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Chaohua Cheng
  • Publication number: 20100090230
    Abstract: It is an object of the present invention to provide a crystal silicon element emitting a desired visible light at high efficiency, by markedly enhancing the crystallinity of the nano Si. A p-type single crystal silicon substrate 10, a thick silicon oxide film 17a and a thin silicon oxide film 17b are disposed on the one surface of the silicon substrate 10. On the thin silicon oxide film 17b, plural nano Si 15 having the same crystal axis as the silicon substrate 10 are formed. In addition, a thin silicon oxide film 16 that is disposed in a manner that the thin silicon film 16 covers the upper and side faces of the nano Si 15, and a transparent electrode (for example ITO) 19 that is disposed in a manner that the transparent electrode 19 covers at least the upper face of the nano Si 15 are formed. Further, a metal electrode 18 (for example, aluminum) is formed in a manner that the metal electrode 18 has an ohmic contact with the other surface of the silicon substrate 10.
    Type: Application
    Filed: August 1, 2006
    Publication date: April 15, 2010
    Inventor: Hideo Honma
  • Publication number: 20090289322
    Abstract: In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 26, 2009
    Inventors: Seong-Ho Moon, Hong-Sik Yoon, Subramanya Mayya, Sun-Woo Lee, Dong-Woo Kim, Xiaofeng Wang
  • Patent number: 7615839
    Abstract: Since VF and IR characteristics of a Schottky barrier diode are in a trade-off relationship, there has heretofore been a problem that an increase in a leak current is unavoidable in order to realize a low VF. Moreover, there has been a known structure which suppresses the leak current in such a manner that a depletion layer is spread by providing P+ regions and a pinch-off effect is utilized. However, in reality, it is difficult to completely pinch off the depletion layer. P+ type regions are provided, and a low VF Schottky metal layer is allowed to come into contact with the P+ type regions and depletion regions therearound. A low IR Schottky metal layer is allowed to come into contact with a surface of a N type substrate between the depletion regions. When a forward bias is applied, a current flows through the metal layer of low VF characteristic. When a reverse bias is applied, a current path narrowed by the depletion regions is formed only in the metal layer portion of low IR characteristic.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: November 10, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tadaaki Souma, Tadashi Natsume
  • Patent number: 7612426
    Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: November 3, 2009
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20090194838
    Abstract: Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Prakash Pendharkar, Eugen Pompiliu Mindricelu
  • Patent number: 7476956
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: January 13, 2009
    Assignee: Cree, Inc.
    Inventors: Primit Parikh, Umesh Mishra