Abstract: A semiconductor integrated circuit device is fabricated on a lightly doped n-type substrate, and p-type wells are formed in the silicon wherein a heavily doped n-type channel stopper is formed in a surface portion between the p-type wells for restricting a parasitic channel between the p-type wells, and the surface portion is doped at a predetermined impurity concentration larger than a remaining portion of the silicon substrate and smaller than the channel stopper so that a p-n junction hardly takes place between the inverted surface portion and the channel stopper.

Abstract: A semiconductor device including a substrate, a semiconductor element formed on the substrate, a terminal formed on the substrate and electrically connected to the semiconductor element, and a protective resistor formed on the substrate and electrically connected between the semiconductor element and the terminal. The resistor is composed of a ferromagnetic magnetoresistive material including Ni alloy. The device may be extended to detect magnetism by adding a magnetoresistive element composed of a ferromagnetic magnetoresistive material including the same Ni alloy as for the protective resistor and deposited at the same time. The device is superior in an anti-noise characteristic and is integrated. Furthermore, the device for detecting magnetism is formed with a lower cost.

Abstract: This invention relates to a semiconductor device comprising an N-type semiconductor substrate, an intermediate breakdown voltage part comprised of a first P-type diffusion layer formed in the N-type semiconductor substrate, a high breakdown voltage part comprised of a second P-type diffusion layer formed in the N-type semiconductor substrate, and a transistor circuit part formed in the N-type semiconductor substrate. According to the invention, a semiconductor device capable of simultaneously forming plural functioning devices in a single semiconductor substrate, causing hardly any short channel effect, is obtained.

Abstract: Emitter-base protection for a first bipolar transistor formed as part of a BiCMOS circuit. A second bipolar transistor is formed in the same well as the first bipolar transistor with both transistors using the well as their collectors. A current path through the collector-emitter of the second transistor provides current to the base of the first transistor maintaining the emitter-to-base voltage of the first transistor at a relatively low reverse potential.

Abstract: In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.

Abstract: A PIN diode with a low voltage peak at the switching on comprises a P-type anode region (4) formed on a first surface of a low doped N-type substrate (1) and a cathode region (2) formed on the second surface of the substrate. The PIN diode comprises on a portion of the first surface an additional N.sup.+ -type region (7) in contact with the anode region for forming a junction with the latter. The additional region is connected to the cathode region.