With Electric Field Controlling Semiconductor Layer Having A Low Enough Doping Level In Relationship To Its Thickness To Be Fully Depleted Prior To Avalanche Breakdown (e.g., Resurf Devices) Patents (Class 257/492)
  • Patent number: 10680059
    Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 9, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10615251
    Abstract: A semiconductor substrate is easily warped by the shrink of the insulating film formed within the deep trench according to the thermal processing in the super junction structure. In order to solve the above problem, in a semiconductor device, an element region and a terminal region are defined on one main surface of the semiconductor substrate. The terminal region is arranged to surround the element region. In the terminal region, a plurality of buried insulators are formed from the main surface of the semiconductor substrate in a way of penetrating an n-type diffusion layer and an n-type column layer and arriving at an n-type epitaxial layer. The buried insulator is formed within a deep trench. The plural buried insulators are arranged in island shapes mutually at a distance from each other.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Yoshida, Tsuyoshi Kachi
  • Patent number: 10573743
    Abstract: A semiconductor device includes a first semiconductor region, a second semiconductor region, an insulating film, and first and second electrodes provided on the insulating film. The insulating film includes first to fourth portions. The first portion is disposed in a region including the region directly above the first semiconductor region. The second portion is disposed at a portion of the region directly above the second semiconductor region. The second portion is thicker than the first portion. The third portion is thinner than the second portion and thicker than the first portion. The fourth portion is thicker than the third portion. The first electrode is disposed in at least a region directly above the first portion. The second electrode is disposed in at least a region directly above the third portion.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 25, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Daisuke Shinohara
  • Patent number: 10249752
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Patent number: 10229993
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure including (a) a base layer, (b) a p-type reduced surface field effect (RESURF) layer disposed over the base layer in a thickness direction, (c) a p-body disposed over the p-type RESURF layer in the thickness direction, (d) a source p+ region and a source n+ region each disposed in the p-body, (e) a high-voltage n-type laterally-diffused drain (HVNLDD) disposed adjacent to the p-body in a lateral direction orthogonal to the thickness direction, the HVNLDD contacting the p-type RESURF layer, and (f) a drain n+ region disposed in the HVNLDD. The LDMOS transistor further includes (a) a first dielectric layer disposed on the silicon semiconductor structure in the thickness direction over at least part of the p-body and the HVNLDD and (b) a first gate conductor disposed on the first dielectric layer in the thickness direction.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 12, 2019
    Assignee: Maxin Integrated Products, Inc.
    Inventors: John Xia, Marco A. Zungia, Badredin Fatemizadeh
  • Patent number: 10115812
    Abstract: A semiconductor device includes a drift region of a first conductivity type, an anode region of a second conductivity type situated below the drift region, an inversion region of the second conductivity type situated above the drift region, an enhancement region of the first conductivity type situated between the drift region and the inversion region, first and second control trenches extending through the inversion region and the enhancement region into the drift region, each control trench being bordered by a cathode diffusion region of the first conductivity type, and a superjunction structure situated in the drift region between the first and the second control trenches so that the superjunction structure does not extend under either the first or the second control trench. The superjunction structure is separated from the inversion region by the enhancement region and includes alternating regions of the first and the second conductivity types.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Patent number: 10062753
    Abstract: A semiconductor device includes a semiconductor substrate having a drift layer, a base layer, a collector layer and a cathode layer. The semiconductor substrate includes a cell region and an outer peripheral region surrounding the cell region. The cell region includes an IGBT region and a diode region. The semiconductor substrate further includes a damage region arranged in the diode region and a part of the outer peripheral region adjacent to a boundary between the outer peripheral region and the diode region. A length, in a longitudinal direction of the diode region, of the part of the outer peripheral region, in which the damage region is arranged, is equal to or more than twice of a thickness of the semiconductor substrate. As a result, recovery characteristic is improved in a portion of the diode region adjacent to the boundary between the outer peripheral region and the diode region.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: August 28, 2018
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno
  • Patent number: 10056450
    Abstract: A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an IGBT device is an IGBT region and a region operating as a diode device is a diode region, the IGBT and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a surface portion of the diode region in the semiconductor substrate. The IGBT and diode regions are demarcated by a boundary between the collector and cathode layers; and a surface portion of the IGBT region includes: a portion having the damaged region at a boundary side with the diode region; and another portion without the damaged region arranged closer to an inner periphery side relative to the boundary side.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 21, 2018
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno
  • Patent number: 9972677
    Abstract: Methods of forming a power semiconductor device are provided in which a semiconductor drift layer that is doped with impurities having a first conductivity type is formed on a semiconductor substrate. A portion of the semiconductor drift layer is removed to form a recessed region in the semiconductor drift layer and to define a first semiconductor pillar. Impurities having a second conductivity type that is opposite the first conductivity type are implanted into a first sidewall of the semiconductor drift layer that is exposed by the recessed region to convert a portion of the first semiconductor pillar into a second semiconductor pillar. A third semiconductor pillar is formed in the recessed region.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 15, 2018
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Daniel J. Lichtenwalner
  • Patent number: 9865702
    Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 9, 2018
    Assignee: CSMC Technologies Fab2 Co., Ltd.
    Inventors: Feng Huang, Guangtao Han, Guipeng Sun, Feng Lin, Longjie Zhao, Huatang Lin, Bing Zhao, Lixiang Liu, Liangliang Ping, Fengying Chen
  • Patent number: 9865677
    Abstract: Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: January 9, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Hyuk Woo, Dae Byung Kim, Chang Yong Choi, Ki Tae Kang, Kwang Yeon Jun, Moon Soo Cho, Soon Tak Kwon
  • Patent number: 9842896
    Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone formed in the substrate adjacent to the first well zone, a gate oxide layer formed on the first well zone and the second well zone, a gate formed on the gate oxide layer, an insulation region formed on the surface of the second well zone, a first implant region formed in the second well zone underneath the insulation region, a second implant region formed below the first implant region, and a junction formed between the first implant region and the second implant region. At least one of the first implant region and the second implant region includes at least two sub-implant regions having different implant concentrations. The sub-implant region having the higher implant concentration is adjacent to the junction.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 12, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Hao Ho, Wen-Hsin Lin, Shin-Cheng Lin
  • Patent number: 9825035
    Abstract: A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first trench, wherein the first trench is formed partially through the first buried layer, and wherein a dielectric layer and the first gate are in the first trench, a second gate in a second trench, wherein the second trench is formed partially through the first buried layer, and wherein the second trench is of a same depth as the first trench, a first drain/source region and a second drain/source region formed on opposite sides of the first trench and a first lateral transistor comprising a second buried layer formed over the substrate, a second well over the second buried layer and drain/source regions over the second well.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: November 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 9768295
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: September 19, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Patent number: 9761676
    Abstract: A power semiconductor device is disclosed. The power semiconductor device includes an upper drift region situated over a lower drift region, a field electrode embedded in the lower drift region, the field electrode not being directly aligned with a gate trench in a body region of the power semiconductor device, where respective top surfaces of the field electrode and the lower drift region are substantially co-planar. A conductive filler in the field electrode can be substantially uniformly doped, and the field electrode is in direct electrical contact with the upper drift region.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Timothy D. Henson
  • Patent number: 9590030
    Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: March 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 9577080
    Abstract: A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Holger Huesken, Frank Dieter Pfirsch, Hans-Joachim Schulze
  • Patent number: 9443972
    Abstract: A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface and forming at least one first trench in the dielectric layer. The at least one first trench extends to the semiconductor body and defines a dielectric mesa region in the dielectric layer. The method further includes forming a second trench in the dielectric mesa region distant to the at least one first trench, forming a semiconductor layer on uncovered regions of the semiconductor body in the at least one first trench and forming a field electrode in the second trench.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies Austria AG
    Inventor: Oliver Blank
  • Patent number: 9437728
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 9401401
    Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a source region disposed apart from a drain region, a first body region surrounding the source region, a deep well region disposed below the drain region, and a second body region disposed below the first body region. A bottom surface of the second body region is not coplanar with a bottom surface of the deep well region, and the first body region has a different conductivity type from the second body region.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: July 26, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, I-Shan Sun, Youngbae Kim, Youngju Kim, Kwangil Kim, Intaek Oh, Jinwoo Moon
  • Patent number: 9385185
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate and a transistor on the substrate. The semiconductor devices may include a first guard ring of first conductivity type in the substrate adjacent the transistor. The semiconductor devices may include a second guard ring of second conductivity type opposite the first conductivity type in the substrate adjacent the first guard ring. Related semiconductor systems are also provided.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: July 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Chang, Dong-Eun Jang
  • Patent number: 9379225
    Abstract: A semiconductor device in which an IGBT region and a diode region are formed on one semiconductor substrate is disclosed. The IGBT region includes: a body layer of a first conductivity type that is formed on a front surface of the semiconductor substrate; a body contact layer of the first conductivity type that is partially formed on a front surface of the body layer and has a higher impurity concentration of the first conductivity type than the body layer; an emitter layer of a second conductivity type that is partially formed on the front surface of the body layer; a drift layer; a collector layer; and a gate electrode. In the semiconductor device, a part of the body contact layer placed at a long distance from the diode region is made larger than a part of the body contact layer placed at a short distance from the diode region.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 28, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keisuke Kimura, Satoru Kameyama, Masaki Koyama, Sachiko Aoi
  • Patent number: 9356135
    Abstract: To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same. In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 31, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kosuke Yoshida, Tetsuya Nitta
  • Patent number: 9349811
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, and an insulating film formed on the principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, the first boundary region including a boundary between a well layer and a RESURF layer, the second boundary region including a boundary between the RESURF layer and a first impurity region. The semiconductor device further includes a plurality of lower field plates formed in the insulating film in such a manner that the plurality of lower field plates do not lie directly above the first and second boundary regions, and a plurality of upper field plates formed on the insulating film in such a manner that the plurality of upper field plates do not lie directly above the first and second boundary regions.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 24, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tetsuo Takahashi
  • Patent number: 9324861
    Abstract: A semiconductor device has on a semiconductor layer: a gate insulating film formed, extending from a second emitter region toward a buffer region beyond a first body region, and covering part of a drift region; and a gate electrode. The second emitter region contacts a first emitter region, and extends laterally to a portion under the gate electrode so as to be longer than a diffusion depth of the second emitter region and not beyond a lateral length of the first body region under the gate electrode, in an area from an end portion of the first emitter region closer to the gate electrode to a region under the gate electrode.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 26, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Teruhisa Ikuta, Akira Fukumoto
  • Patent number: 9306002
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: April 5, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Shusaku Fujie
  • Patent number: 9287384
    Abstract: A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: March 15, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 9257541
    Abstract: A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p+-type diffusion region, a p?-type region, and an anode electrode. The p?-type region is formed as a region of relatively high electrical resistance sandwiched between the p+-type diffusion regions.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: February 9, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiko Otsuki, Koji Sadamatsu, Yasuhiro Yoshiura
  • Patent number: 9209277
    Abstract: Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Tahir A. Khan, Bernhard H. Grote, Vishnu K. Khemka, Ronghua Zhu
  • Patent number: 9202936
    Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 1, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akito Nishii, Katsumi Nakamura
  • Patent number: 9196721
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 9196680
    Abstract: A laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) includes: a source contact region, a gate contact region, a drain contact region, and an n-type buried layer. The LDMOSFET also includes a p-type body region formed in an n-type epitaxial layer, the p-type body region directly contacting the source contact region and extending past an end of the source contact region toward the drain contact region. The LDMOSFET also includes a p-type reduced surface field (PRSF) region formed in the n-type epitaxial layer, the PRSF region disposed between the p-type body region and the n-type buried layer. The LDMOSFET also includes an n-type drift region formed in the n-type epitaxial layer, the n-type drift region directly contacting the drain contact region. The LDMOSFET also includes an n-type diffusion region in the n-type epitaxial layer, the n-type diffusion region electrically connecting the n-type buried layer with the n-type drift region.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 24, 2015
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Vishnu Khemka, Ronghua Zhu, Tahir Arif Khan, Vijay Parthasarathy
  • Patent number: 9196681
    Abstract: A laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) includes a p-type body region formed in an n-type epitaxial layer, the p-type body region directly contacting a source contact region and extending past an end of the source contact region toward a drain contact region. The LDMOSFET also includes a p-type reduced surface field (PRSF) region formed in the n-type epitaxial layer, the PRSF region disposed between the p-type body region and the n-type buried layer. The LDMOSFET also includes an n-type drain drift region formed in the n-type epitaxial layer, the n-type drain drift region directly contacting the drain contact region. The LDMOSFET also includes an n-type drift region formed in the n-type epitaxial layer, the n-type drift region directly contacting the n-type drain drift region.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 24, 2015
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Vishnu Khemka, Ronghua Zhu, Tahir Arif Khan, Vijay Parthasarathy
  • Patent number: 9054180
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate and a transistor on the substrate. The semiconductor devices may include a first guard ring of first conductivity type in the substrate adjacent the transistor. The semiconductor devices may include a second guard ring of second conductivity type opposite the first conductivity type in the substrate adjacent the first guard ring. Related semiconductor systems are also provided.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: June 9, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Chang, Dong-Eun Jang
  • Patent number: 9035415
    Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 19, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Patent number: 9024383
    Abstract: A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Gamerith, Armin Willmeroth, Franz Hirler
  • Patent number: 9006822
    Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 14, 2015
    Assignee: NXP B.V.
    Inventors: Steven Thomas Peake, Phil Rutter
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 9000538
    Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Murakawa
  • Patent number: 8994141
    Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Takami Otsuki
  • Patent number: 8981477
    Abstract: A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 8963242
    Abstract: A power semiconductor device includes first to fifth electrodes, first to sixth semiconductor layers, and several first pillar layers. The first semiconductor layer is formed on the first electrode. The second semiconductor layer is formed on the first semiconductor layer. Several first pillar layers are arranged parallel with the second semiconductor layer. The third and fourth semiconductor layers are formed on the second semiconductor layer. The fourth electrode is formed on the first pillar layer adjacent to the third semiconductor layer. The fifth electrode is formed on the first pillar layer adjacent to the fourth semiconductor layer. The concentration of dopant of the first pillar layer positioning between the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode is lower than the concentration of dopant of the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Saito
  • Patent number: 8963245
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Patent number: 8957475
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 8946851
    Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Joel Montgomery McGregor, Vishnu Khemka
  • Patent number: 8940609
    Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 27, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 8941207
    Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 27, 2015
    Assignee: University of Electronic Science and Technology
    Inventor: Xingbi Chen
  • Patent number: 8928075
    Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, Marie Denison, Taylor Efland
  • Patent number: 8916913
    Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 23, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ji-Hyoung Yoo, Lei Zhang
  • Patent number: 8907419
    Abstract: A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu