With Electric Field Controlling Semiconductor Layer Having A Low Enough Doping Level In Relationship To Its Thickness To Be Fully Depleted Prior To Avalanche Breakdown (e.g., Resurf Devices) Patents (Class 257/493)
  • Patent number: 10930732
    Abstract: A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H+ (proton) than a concentration of a lifetime killer impurity in the first region.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 23, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Mitsuhiro Kushibe, Tatsuo Shimizu
  • Patent number: 10910377
    Abstract: Laterally-diffused-metal-oxide-silicon (LDMOS) devices, integrated circuits including LDMOS devices, and methods for fabricating the same are provided. An exemplary LDMOS device includes a substrate having a surface, a gate structure overlying the surface and a channel region in the substrate below the gate structure, and a drain region in the substrate. The LDMOS device further includes a surface insulator region disposed between the gate structure and the drain region at the surface of the substrate and a dielectric block different from the surface insulator region and located over the surface insulator region. Also, the LDMOS device includes a field effect structure. The field effect structure includes a field plate disposed over and distanced from the surface of the substrate. The field effect structure also includes a conductive structure coupled to the field plate and extending from the field plate toward the dielectric block.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei Zhang
  • Patent number: 10872925
    Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Ryan Green, Rajni J. Aggarwal, Ajit Sharma
  • Patent number: 10868111
    Abstract: A semiconductor device includes a plurality of broad buffer layers provided in a drift layer. Each of the plurality of the broad buffer layers has an impurity concentration exceeding that of a portion of the drift layer excluding the broad buffer layers, and has a mountain-shaped impurity concentration distribution in which a local maximum value is less than the impurity concentration of an anode layer and a cathode layer. The plurality of broad buffer layers are disposed at different depths from a first main surface of the drift layer, respectively, the number of broad buffer layers close to the first main surface from the intermediate position of the drift layer is at least one, and number of broad buffer layers close to a second main surface of the drift layer from the intermediate position of the drift layer is at least two. The broad buffer layer includes a hydrogen-related donor.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Patent number: 10861932
    Abstract: A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ze Chen, Kazuhiro Shimizu
  • Patent number: 10854762
    Abstract: A semiconductor device includes an n-type drift layer formed on a semiconductor substrate having an off-angle, plurality of p-type pillar regions formed in the drift layer, and a surface electrode formed on the drift layer including the plurality of p-type pillar regions. A plurality of withstand voltage holding structures which are p-type semiconductor regions are formed in a surface layer of the drift layer including the plurality of p-type pillar regions to surround an active region. Each of the plurality of p-type pillar regions has a linear shape extending in a direction of the off-angle of the semiconductor substrate. Each of the plurality of withstand voltage holding structures has a frame-like shape including sides extending in parallel with the plurality of p-type pillar regions and sides perpendicular to the plurality of p-type pillar regions in a planar view.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 1, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Ebihara, Masayuki Furuhashi, Takanori Tanaka
  • Patent number: 10840326
    Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a first semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a third semiconductor layer of the second conductivity type in the active region and a third semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the third semiconductor layer, and the second semiconductor layer is not in contact with a surface of the first semiconductor layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Yasuhiko Oonishi, Masanobu Iwaya
  • Patent number: 10686068
    Abstract: A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Noboru Morimoto
  • Patent number: 10636868
    Abstract: A semiconductor device includes a plurality of broad buffer layers provided in a drift layer. Each of the plurality of the broad buffer layers has an impurity concentration exceeding that of a portion of the drift layer excluding the broad buffer layers, and has a mountain-shaped impurity concentration distribution in which a local maximum value is less than the impurity concentration of an anode layer and a cathode layer. The plurality of broad buffer layers are disposed at different depths from a first main surface of the drift layer, respectively, the number of broad buffer layers close to the first main surface from the intermediate position of the drift layer is at least one, and number of broad buffer layers close to a second main surface of the drift layer from the intermediate position of the drift layer is at least two. The broad buffer layer includes a hydrogen-related donor.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Patent number: 10593751
    Abstract: An object of the present invention is to provide a semiconductor device capable of satisfactorily securing a breakdown voltage not only in a cell region but also in an edge termination region in a super junction structure. A semiconductor device according to the present invention includes a drift region of a first conductivity type and a pillar region of a second conductivity type a RESURF layer formed across a plurality of the pillar regions in an edge termination region and extending in the thickness direction from surfaces of the drift region and the pillar region, and a high-concentration region of the second conductivity type formed in a surface of the RESURF layer, the high-concentration region being higher in impurity concentration than the RESURF layer, no pillar region being formed under the high-concentration region in the thickness direction.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 17, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Kohei Ebihara
  • Patent number: 10586846
    Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
  • Patent number: 10566450
    Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 18, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Giuseppe Greco, Fabrizio Roccaforte
  • Patent number: 10483358
    Abstract: A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 19, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou Tan, Gangyi Hu, Zhaohuan Tang, Jianan Wang, Yonghui Yang, Yi Zhong, Yang Cao, Yong Liu, Kunfeng Zhu
  • Patent number: 10388775
    Abstract: A semiconductor device of the present invention is structured such that in a surface layer of a first principal surface of a semiconductor substrate, an n-type drift layer, a p-type base layer, a p-type floating layer, an n-type emitter layer, an emitter electrode, and a trench in which a gate electrode is embedded with a gate insulating film is disposed therebetween are formed from a front surface side. Further, in a surface layer of a second principal surface of the semiconductor substrate, a p-type collector layer and a collector electrode contacting the-type collector layer are formed, and in a direction from the p-type collector layer toward a surface, an n-type selenium-doped field stop layer and an n-type proton doped field stop layer are formed, whereby IGBT turn OFF oscillation, oscillation at diode reverse recovery, and increases in leak voltage can be suppressed, and electrical loss can be reduced.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 20, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 10388735
    Abstract: The present disclosure provides a semiconductor device including a substrate, an n? type layer, an n+ type region, a p type region, a p+ type region, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode, wherein the n+ type region is disposed at a left side and a right side of the n? type layer in a plan view and configured to form in a striped pattern in a plan view, wherein the p+ type region is disposed at an outer surface of the n+ type region in a plan view and configured to form in a striped pattern in a plan view, wherein the p type region is disposed at an inner surface the n+ type region in a plan view and is separated by a predetermined interval along a longitudinal direction of the n+ type region in a plan view.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 20, 2019
    Assignees: Hyundai Motor Company, KIA Motors Corporation
    Inventor: Dae Hwan Chun
  • Patent number: 9899508
    Abstract: Embodiments are directed to super-junction semiconductor devices having an inactive region positioned between active cells. In one embodiment, a semiconductor device is provided that includes a substrate and a drain region on the substrate. The drain region has a first conductivity type. A plurality of first columns is disposed on the drain region, with the first columns having the first conductivity type. A plurality of second columns is disposed on the drain region, with the second columns having a second conductivity type. The first and second columns are alternately arranged such that each of the second columns is positioned between respective first columns. First and second gate structures are included that overlie respective first columns, and a body region is included that has the second conductivity type. The body region abuts at least two second columns and at least one first column positioned between the at least two second columns.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: February 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Schillaci, Paola Maria Ponzio, Alessandro Angelo Alfio Palazzo
  • Patent number: 9564495
    Abstract: A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm?3 at a first distance to the first surface and does not fall below 1E14 cm?3 over at least 60% of an interval between the first surface and the first distance.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Moriz Jelinek, Werner Schustereder
  • Patent number: 9437420
    Abstract: A capacitor can include a crystallized metal oxide dielectric layer having a first dielectric constant and an amorphous metal oxide dielectric layer, on the crystallized metal oxide dielectric layer, where the amorphous metal oxide dielectric layer has a second dielectric constant that is less than the first dielectric constant and is greater than a dielectric constant of aluminum oxide.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 6, 2016
    Assignees: Samsung Electronics Co., Ltd., NaMLab gGmbH
    Inventors: Kyu-Ho Cho, Youn-Soo Kim, Han-Jin Lim, Steve Knebel, Uwe Schroeder
  • Patent number: 9379180
    Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: June 28, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
  • Patent number: 9362395
    Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: June 7, 2016
    Assignee: ams AG
    Inventor: Martin Knaipp
  • Patent number: 9312346
    Abstract: A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Armin Willmeroth, Michael Rueb, Holger Kapels
  • Patent number: 9240444
    Abstract: A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: January 19, 2016
    Assignee: Nuvoton Technology Corporation
    Inventor: MD Imran Siddiqui
  • Patent number: 9209683
    Abstract: The present disclosure provides a switched voltage converter for receiving a source voltage and producing an output voltage. The voltage converter comprises a switch controller and a switched device communicatively coupled to the switch controller. The switch controller adjusts the output voltage by controlling a duty cycle of the switched device. The switched device is sized such that it is characterized by a drain-to-source breakdown voltage greater than or substantially equal to the source voltage and the output voltage and is further characterized by a hot-carrier injection rating less than the source voltage or the output voltage. In further embodiments, the switched device is sized such that it is characterized by a drain-to-source breakdown voltage greater than or substantially equal to a peak operating voltage and is further characterized by a hot-carrier injection rating less than the peak operating voltage.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Alexander Kalnitsky
  • Patent number: 9153576
    Abstract: A semiconductor substrate comprises an IGBT region and a diode region. The IGBT region comprises: an n-type emitter region; a p-type IGBT body region; an n-type IGBT barrier region; an n-type IGBT drift region; a p-type collector region; a first trench; a first insulating layer; and a first gate electrode. The diode region comprises: a p-type diode top body region; an n-type diode barrier region; a p-type diode bottom body region; an n-type cathode region; a second trench; a second insulating layer; and a second gate electrode. An n-type impurity density of a specific part of the diode barrier region making contact with the second insulating layer is higher than an n-type impurity density of the IGBT barrier region.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: October 6, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Hosokawa, Yusuke Yamashita, Satoru Machida
  • Patent number: 9129936
    Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: September 8, 2015
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 9129802
    Abstract: A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 8, 2015
    Assignee: RF Micro Devices, Inc.
    Inventor: Andrew P. Ritenour
  • Patent number: 9117845
    Abstract: In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: August 25, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher Nassar, Sunglyong Kim, Steven Leibiger, James Hall
  • Patent number: 9105486
    Abstract: A semiconductor device includes a first conductive type semiconductor substrate, a second conductive type active region formed on a top surface side of the semiconductor substrate, a second conductive type inside VLD region formed to contact the active region on the top surface side in a plan view, and a second conductive type well region formed to contact a portion opposite to the portion contacting the active region of the inside VLD region on the top surface side in a plan view. The well region is formed to be deeper than the active region. The inside VLD region has the same depth as that of the active region in the portion contacting the active region, the depth gradually increasing from the active region toward the well region and becoming the same as the depth of the well region in the portion contacting the well region.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: August 11, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Atsushi Narazaki
  • Patent number: 9064714
    Abstract: An N type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a P type epitaxial layer covering a surface of a P type semiconductor substrate to reach the surface of the semiconductor substrate. An N type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region. High breakdown voltage isolation region includes a corner portion located along a corner pattern of rectangular high-side circuit region, and a linear portion located along a linear pattern thereof. The concentration of an impurity in an N type diffusion layer of corner portion is set to be higher than the concentration of an impurity in an N type diffusion layer of linear portion.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 23, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Manabu Yoshino
  • Patent number: 9059282
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: June 16, 2015
    Assignee: Infineon Technologies AG
    Inventors: Uwe Hodel, Andreas Martin, Wolfgang Heinrigs
  • Patent number: 9048115
    Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: June 2, 2015
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu, Gene Sheu, Neelam Agarwal, Karuna Nidhi, Chia-Hao Lee, Rudy Octavius Sihombing
  • Patent number: 9041127
    Abstract: The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Publication number: 20150137306
    Abstract: An N type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a P type epitaxial layer covering a surface of a P type semiconductor substrate to reach the surface of the semiconductor substrate. An N type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region. High breakdown voltage isolation region includes a corner portion located along a corner pattern of rectangular high-side circuit region, and a linear portion located along a linear pattern thereof. The concentration of an impurity in an N type diffusion layer of corner portion is set to be higher than the concentration of an impurity in an N type diffusion layer of linear portion.
    Type: Application
    Filed: September 8, 2014
    Publication date: May 21, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Manabu YOSHINO
  • Patent number: 9035434
    Abstract: A semiconductor device having first and second portions with opposite conductivity types. There are first through fourth layers in the semiconductor device. A peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of a first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion which is located on the second portion. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: May 19, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 9035415
    Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 19, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Publication number: 20150097262
    Abstract: A semiconductor diode includes a semiconductor body and trench structures extending from a surface of the semiconductor body into the semiconductor body. The semiconductor body includes a doped layer of a first conductivity type and a doped zone of a second conductivity type opposite to the first conductivity type. The doped zone is formed between the doped layer and a first surface of the semiconductor body. The trench structures are arranged between electrically connected portions of the semiconductor body. The trench structures do not include conductive structures that are both electrically insulated from the semiconductor body and electrically connected with another structure outside the trench structures.
    Type: Application
    Filed: November 20, 2014
    Publication date: April 9, 2015
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze
  • Patent number: 9000538
    Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Murakawa
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 8994141
    Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Takami Otsuki
  • Publication number: 20150069567
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 12, 2015
    Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, Harold Heidenreich
  • Publication number: 20150060884
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a first electrode. The first semiconductor region is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, and is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region, and is of the second conductivity type. The third semiconductor region contains a first impurity of the first conductivity type and a second impurity of the second conductivity type, and satisfies 1<D2/D1<3, where D1 is a first concentration of the first impurity, and D2 is a second concentration of the second impurity. The first electrode is provided on the first, second, and third semiconductor regions. The first electrode is in contact with the second and third semiconductor regions.
    Type: Application
    Filed: August 25, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chiharu OTA, Tatsuo Shimizu, Johji Nishio, Takashi Shinohe
  • Publication number: 20150054119
    Abstract: A device structure is provided to reduce the leakage current of semiconductor devices with a floating buried layer (FBL), includes a substrate, a first epitaxial layer, a split floating buried layer, a second epitaxial layer, a doped trench, a protected device, a surface junction termination extension (S-JTE) and a scribe street. The device and the S-JTE are designed at the second epitaxial layer and the split floating buried layer at the joint of the first and second epitaxial layers. The doped trench is penetrated through the second epitaxial layer and connected to the split floating buried layer. The substrate, the first and second epitaxial layers feature the same typed doping which is opposite to that of split floating buried layer and doped trench.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 26, 2015
    Inventors: KAI-ZHOU TAN, ZHAO-HUAN TANG, RONG-KAN LIU, YONG LIU
  • Patent number: 8963245
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Publication number: 20150041946
    Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Inventors: Stephan Voss, Alexander Breymesser, Hans-Joachim Schulze, Erich Griebl, Oliver Haeberlen, Andreas Moser
  • Patent number: 8946851
    Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Joel Montgomery McGregor, Vishnu Khemka
  • Patent number: 8928075
    Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, Marie Denison, Taylor Efland
  • Publication number: 20150001668
    Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventor: Mitsuhiko KITAGAWA
  • Patent number: 8916913
    Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 23, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ji-Hyoung Yoo, Lei Zhang
  • Publication number: 20140353794
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 4, 2014
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Publication number: 20140346633
    Abstract: A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Inventors: Akihiro JONISHI, Masaharu YAMAJI