Floating Pn Junction Guard Region Patents (Class 257/495)
  • Patent number: 10396775
    Abstract: Provided is a semiconductor device capable of preventing a malfunction of a high-side gate driver circuit that is caused by a negative voltage surge. A diode is connected between a p-type bulk substrate configuring a semiconductor layer, and a first potential (GND potential), and a signal is transmitted from a control circuit that is formed in an n diffusion region configuring a first semiconductor region through a first level down circuit and a first level up circuit to a high-side gate driver circuit that is formed in an n diffusion region configuring a second semiconductor region. As a result, a malfunction of the high-side gate driver circuit that is caused by a negative voltage surge can be prevented.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akihiro Jonishi, Masashi Akahane
  • Patent number: 10141397
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Ichimura, Satoshi Eguchi, Tetsuya Iida, Yuya Abiko
  • Patent number: 9831144
    Abstract: A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 28, 2017
    Assignee: QUBEICON LTD.
    Inventor: Shimon Podval
  • Patent number: 9786735
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akio Ichimura, Satoshi Eguchi, Tetsuya Iida, Yuya Abiko
  • Patent number: 9583578
    Abstract: A semiconductor portion of a semiconductor device includes a semiconductor layer with a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type. The impurity zone adjoins a first surface of the semiconductor portion in an element area. A connection layer directly adjoins the semiconductor layer opposite to the first surface. At a distance to the first surface an overcompensation zone is formed in an edge area that surrounds the element area. The overcompensation zone and the connection layer have opposite conductivity types. In a direction vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone. In case of locally high current densities, the overcompensation zone injects charge carriers into the semiconductor layer that locally counter a further increase of electric field strength and reduce the risk of avalanche breakdown.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Franz Hirler
  • Patent number: 9536942
    Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 3, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Kenji Hamada, Kohei Ebihara, Akihiko Furukawa, Yuji Murakami
  • Patent number: 9515199
    Abstract: A semiconductor device has a drift region having an upper surface and a lower surface. A first contact is on the upper surface of the drift region and a second contact is on the lower surface of the drift region. The drift region includes a first semiconductor pillar that has a tapered sidewall and that is doped with first conductivity type impurities and a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar, the second semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: December 6, 2016
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Daniel J. Lichtenwalner
  • Patent number: 9385242
    Abstract: TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 5, 2016
    Assignee: Diodes Incorporated
    Inventors: John Earnshaw, Wolfgang Kemper, Yen-Li Lin, Steve Badcock, Mark French
  • Patent number: 9219133
    Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 22, 2015
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 9153674
    Abstract: A semiconductor device is disclosed. One embodiment provides a cell area and a junction termination area at a first side of a semiconductor zone of a first conductivity type. At least one first region of a second conductivity type is formed at a second side of the semiconductor zone. The at least one first region is opposed to the cell area region. At least one second region of the second conductivity type is formed at the second side of the semiconductor zone. The at least one second region is opposed to the cell area region and has a lateral dimension smaller than the at least first region.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 6, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans-Joachim Schulze
  • Publication number: 20150137220
    Abstract: The present disclosure discloses a field effect transistor (“FET”), a termination structure and associated method for manufacturing. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench and a guard ring region located underneath the bottom of the termination trench in the semiconductor layer. Each termination trench is lined with a termination insulation layer, and is filled with a first conductive spacer and a second conductive spacer respectively against an inner sidewall and an outer sidewall of the termination trench and spaced apart from each other with a space, and a dielectric layer filling the space between the first and the second spacers.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Tiesheng Li, Rongyao Ma
  • Publication number: 20150130014
    Abstract: The present disclosure provides a rectifier. The rectifier includes a N-type epitaxial layer, a plurality of P-type diffusion regions and a plurality of N-type diffusion regions. The P-type diffusion regions are disposed in the N-type epitaxial layer, and the N-type diffusion regions are respectively disposed in the P-type diffusion regions. Wherein, the P-type diffusion regions are electronically coupled to the N-type diffusion regions.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: SUMPRO ELECTRONICS CORPORATION
    Inventor: Wei-Fan Chen
  • Patent number: 8994141
    Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Takami Otsuki
  • Patent number: 8981385
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view. The semiconductor element portion includes a drift region having a first conductivity type. The termination region includes a first electric field relaxing region contacting the element region and having a second conductivity type different from the first conductivity type, and a second electric field relaxing region arranged outside the first electric field relaxing region as viewed in the plan view, having the second conductivity type, and spaced from the first electric field relaxing region. A ratio calculated by dividing a width of the first electric field relaxing region by a thickness of the drift region is not less than 0.5 and not more than 1.83.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8952393
    Abstract: A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration NA. A relaxation region is provided in a portion of the second surface of the first drift layer. The first drift layer and the second drift layer form a drift region in which the relaxation region is buried. The second drift layer has an impurity concentration NB, NB>NA being satisfied. A body region, a source region, and a second electrode are provided on the second drift layer.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: February 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8933532
    Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 13, 2015
    Assignee: Avogy, Inc.
    Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
  • Patent number: 8916931
    Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake
  • Patent number: 8866222
    Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Stefan Gamerith, Franz Hirler
  • Patent number: 8841744
    Abstract: A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n? epitaxial layer between a bootstrap diode Db and a p-type GND region at the ground potential (GND). The p-type floating region extends to the cavity for suppressing the leakage current caused by the holes flowing to the p? substrate in charging an externally attached bootstrap capacitor C1. The semiconductor apparatus which includes a bootstrap-type driver circuit facilitates suppressing the leakage current caused by the holes flowing to the p? substrate, when the bootstrap diode is biased in forward.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: September 23, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomohiro Imai, Masaharu Yamaji
  • Patent number: 8822316
    Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Atsuya Masada, Mitsuo Horie
  • Publication number: 20140239436
    Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: March 26, 2014
    Publication date: August 28, 2014
    Applicant: Alpha & Omega Semiconductor Incorporated
    Inventors: Jun Hu, Karthik Padmanabhan, Madhur Bobde, Hamza Yilmaz
  • Patent number: 8809969
    Abstract: A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 19, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Tarui, Atsushi Narazaki, Ryoichi Fujii
  • Patent number: 8803252
    Abstract: A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance Ld from the first main surface. The relaxing region has a second conductivity type and has an impurity dose amount Drx. The drift layer has an impurity concentration Nd between the first main surface and the relaxing region. Relation of Drx>Ld·Nd is satisfied. Thus, a silicon carbide semiconductor device having a high breakdown voltage is provided.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8786045
    Abstract: In one general aspect, a termination structure can include a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type where the plurality of pillars define a plurality of concentric rings surrounding an active area of a semiconductor device. The termination structure can include a conductive field plate where the plurality of pillars includes a first pillar coupled to the conductive field plate. The termination structure can include a dielectric layer where the plurality of pillars include a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: July 22, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Jaegil Lee, Jinyoung Jung, Hocheol Jang
  • Patent number: 8716826
    Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: May 6, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Ryouichi Kawano, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
  • Patent number: 8686532
    Abstract: A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silicon substrate 101; and an annular seal ring 105 consisting of a first conductive ring 125 to a sixth conductive ring 145 buried in the first insulating film 123 to the sixth insulating film 143, which surrounds the periphery of the logic unit and the analog unit 153. In the seal ring region 106, there is formed a pn junction acting as a nonconducting part 104, which blocks conduction in a path from the logic unit, through the seal ring 105 to the analog unit 153.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 8664723
    Abstract: A structure includes an isolation ring at a top surface of a substrate. A well region of a first conductivity type is in a surface portion of the substrate. The well region includes a first portion having a top portion encircled by the isolation ring, and a second portion having a top portion encircling the isolation ring. A base resistance tuning ring includes a portion overlapped by the isolation ring, wherein the base resistance tuning ring is between the first portion and the second portion of the well region. The base resistance tuning ring is selected from the group consisting essentially of a ring of the first conductivity type, a substantially neutral ring, and a ring of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chou Tseng, Wun-Jie Lin
  • Publication number: 20140015090
    Abstract: A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8580644
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 8564088
    Abstract: In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: October 22, 2013
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8558315
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 15, 2013
    Assignee: PFC Device Corporation
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kou-Liang Chao
  • Patent number: 8541839
    Abstract: A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A second electrode is electrically connected to a second zone of the semiconductor body. Furthermore, the semiconductor body has a drift path region, which is arranged in the semiconductor body between the first electrode and the second electrode. A cell region of the semiconductor component is subdivided into a main cell region and an auxiliary cell region, wherein the breakdown voltage of the auxiliary cells is greater than the breakdown voltage of the main cells.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: September 24, 2013
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Publication number: 20130234201
    Abstract: A field stop structure is disclosed. The field stop structure is divided into a three-dimensional structure by a plurality of trenches formed on a back side of a silicon substrate and hence obtains a greater formation depth in the substrate and can achieve a higher ion activation efficiency. Moreover, a first electrode region of a fast recovered diode (FRD) is formed in the trenches, thereby enabling the integration of a FRD with an insulated gate bipolar transistor (IGBT) device. Methods for forming field stop structure and reverse conducting IGBT semiconductor device are also disclosed.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 12, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Shengan Xiao
  • Patent number: 8487372
    Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 16, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8415765
    Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 9, 2013
    Assignee: Panasonic Corporation
    Inventors: Atsuya Masada, Mitsuo Horie
  • Patent number: 8362585
    Abstract: A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: January 29, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Anup Bhalla, Ji Pan, Daniel Ng
  • Patent number: 8357985
    Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: January 22, 2013
    Assignee: Analog Devices, Inc.
    Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson
  • Patent number: 8350352
    Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: January 8, 2013
    Assignee: Analog Devices, Inc.
    Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson
  • Patent number: 8350366
    Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 8, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventor: Bernhard Koenig
  • Publication number: 20120267750
    Abstract: A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n? epitaxial layer between a bootstrap diode Db and a p-type GND region at the ground potential (GND). The p-type floating region extends to the cavity for suppressing the leakage current caused by the holes flowing to the p? substrate in charging an externally attached bootstrap capacitor C1. The semiconductor apparatus which includes a bootstrap-type driver circuit facilitates suppressing the leakage current caused by the holes flowing to the p? substrate, when the bootstrap diode is biased in forward.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 25, 2012
    Applicant: FUJI ELECTRONIC CO., LTD.
    Inventors: Tomohiro IMAI, Masaharu Yamaji
  • Patent number: 8274080
    Abstract: A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hyun Han
  • Patent number: 8264038
    Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu, Xinfen Chen
  • Publication number: 20120205666
    Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 16, 2012
    Inventors: Jason Henning, Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 8242572
    Abstract: A semiconductor apparatus includes, below a high-voltage wiring, a p? diffusion layer in contact with an n drain buffer layer and a p+ diffusion layer in contact with a p? diffusion layer for reducing the electric field strength in an insulator film, which the high-voltage wiring crosses over. Reducing electric field strength in the insulator film prevents lowering of breakdown voltage of a high-voltage NMOSFET, break down of an interlayer insulator film, and impairment of isolation breakdown voltage of a device isolation trench. The semiconductor apparatus according to the invention facilitates bridging a high-voltage wiring from a high-voltage NMOSFET and such a level-shifting device to a high-voltage floating region crossing over a device isolation trench without impairing the breakdown voltage of the high-voltage NMOSFET, without breaking down the interlayer insulator film and without impairing the isolation breakdown voltage of the device isolation trench.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: August 14, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Masaharu Yamaji
  • Patent number: 8198651
    Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: June 12, 2012
    Assignee: Infineon Technologies AG
    Inventors: Gernot Langguth, Wolfgang Soldner, Cornelius Christian Russ
  • Patent number: 8178941
    Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: May 15, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Ryouichi Kawano, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
  • Patent number: 8143679
    Abstract: A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. The second silicon region has a recessed portion extending below the first depth and out to an edge of a die housing the semiconductor power device. The recessed portion forms a vertical wall at which the first silicon region terminates. A first conductive electrode extends into the recessed portion and is insulated from the second silicon region.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 8120136
    Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: February 21, 2012
    Assignee: Analog Devices, Inc.
    Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson
  • Patent number: 8110853
    Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 8097919
    Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P?N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P?N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 17, 2012
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal