In Array Patents (Class 257/5)
  • Patent number: 10438655
    Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Jung Hyun Kwon, Yong Ju Kim, Do Sun Hong
  • Patent number: 10431596
    Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 1, 2019
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Patent number: 10403631
    Abstract: Embodiments of three-dimensional (3D) ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a 3D ferroelectric memory device includes a substrate and a plurality of ferroelectric memory cells each extending vertically above the substrate. Each of the ferroelectric memory cells includes a capacitor and a transistor electrically connected to the capacitor. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode. The transistor includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 3, 2019
    Assignee: Wuxi Petabyte Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Yushi Hu, Qian Tao
  • Patent number: 10403817
    Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul-ji Song, Sung-won Kim, Il-mok Park, Jong-chul Park, Ji-Hyun Jeong
  • Patent number: 10388870
    Abstract: Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 20, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Perumal Ratnam, Tanmay Kumar, Christopher Petti
  • Patent number: 10381304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Mark W. Kuemerle
  • Patent number: 10340283
    Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 2, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jung-Yi Guo, Chun-Min Cheng
  • Patent number: 10340447
    Abstract: A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Talia S. Gershon, Seyoung Kim, Dennis M. Newns, Teodor K. Todorov
  • Patent number: 10325653
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
  • Patent number: 10325958
    Abstract: A memory device includes a first interconnect extending in a first direction, semiconductor members extending in a second direction, a second interconnect provided between the semiconductor members and extending in a third direction, a first insulating film provided between the semiconductor member and the second interconnect, third interconnects extending in the second direction, fourth interconnects provided between the third interconnects and arranged along the second direction, a resistance change film provided between the third interconnect and the fourth interconnects, and a first film. The first film is provided between the second interconnect and the fourth interconnect, interposes between the semiconductor member and the resistance change film, and not interpose between the semiconductor member and the third interconnect connected to each other. A first end of the semiconductor member is connected to the first interconnect.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro Noda, Mutsumi Okajima
  • Patent number: 10269433
    Abstract: A memory device according to an embodiment includes word lines stacked in a third direction perpendicular to a first direction and a second direction; main bit lines including a first main bit line and extending in the second direction; transistors including first and second transistors of which the channel width is greater than the width of the main bit lines; sub-bit lines extending in the third direction and including a first sub-bit line electrically connected to the first main bit line, with the first transistor interposed therebetween, and a second sub-bit line electrically connected to the first main bit line, with the second transistor interposed therebetween, and being adjacent to the first sub-bit line, a line segment virtually connecting the first sub-bit line and the second sub-bit line intersecting the second direction; and a resistance-change layer provided between the word lines and the sub-bit lines.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mutsumi Okajima
  • Patent number: 10229920
    Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Qintao Zhang, Juntao Li, Geng Wang
  • Patent number: 10217799
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 10199568
    Abstract: According to one embodiment, a magnetic storage device includes a substrate, a dummy contact disposed on a top surface of the substrate, extending linearly in a direction substantially perpendicular to the top surface of the substrate, and floating electrically, and a magnetoresistive effect element included in a layer and insulated from the dummy contact, wherein the layer is disposed on the top surface of the dummy contact.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Nagamine, Young Min Eeh, Daisuke Watanabe, Kazuya Sawada, Toshihiko Nagase
  • Patent number: 10186554
    Abstract: Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Yuan Sun, Elgin Kiok Boone Quek, Shyue Seng Tan, Xuan Anh Tran
  • Patent number: 10180820
    Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 15, 2019
    Assignee: HEWLETT PACKARD ENTERPRlSE DEVELOPMENT LP
    Inventors: Brent Buchanan, Le Zheng, John Paul Strachan
  • Patent number: 10176869
    Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 8, 2019
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Marcella Carissimi, Vikas Rana
  • Patent number: 10153433
    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli, Carmela Cupeta, Fabio Pellizzer
  • Patent number: 10147764
    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Andrea Redaelli
  • Patent number: 10128313
    Abstract: In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Tsai Chen, Wenhsien Kuo, Meng-Chun Shih, Ching-Huang Wang, Chia-Fu Lee, Yu-Der Chih
  • Patent number: 10115897
    Abstract: A resistive memory device includes an alternating stack of insulating layers and electrically conductive layers. Sidewalls of the electrically conductive layers are laterally recessed relative to sidewalls of the insulating layers to define laterally recessed regions. Discrete clam-shaped barrier material portions are located within the laterally recessed regions. Middle electrodes include a protrusion portion embedded within a respective one of the discrete clam shaped barrier material portions and a vertically-extending portion located outside the laterally recessed regions and having a greater vertical extent than the embedded portion. A resistive memory material layer contacts the vertically-extending portion of each of the middle electrodes. A vertical conductive line contacts the resistive memory material layer.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yoshihiro Sato
  • Patent number: 10109681
    Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 23, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luiz M. Franca-Neto, Jeffrey Lille
  • Patent number: 10103324
    Abstract: A memory device includes a plurality of bit lines, including first and second bit lines, extending in a first direction away from a substrate, a plurality of word lines, including first and second word lines, extending in a second direction crossing the first direction and substantially parallel to a surface of the substrate, a first variable resistance film between the first word line and the first bit line and a second variable resistance film between the second word line and the second bit line, an insulating material electrically isolating the first and second word lines and the first and second bit lines, and a plurality of air gaps between the first and second bit lines.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 16, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kunifumi Suzuki, Kazuhiko Yamamoto
  • Patent number: 10096655
    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli
  • Patent number: 10074694
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Patent number: 10056546
    Abstract: Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew Joseph BrightSky, SangBum Kim, Chung Hon Lam, Norma Edith Sosa
  • Patent number: 10049736
    Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 14, 2018
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Marcella Carissimi, Vikas Rana
  • Patent number: 10038032
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Toshiyuki Sasaki
  • Patent number: 10032789
    Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dohyun Lee, Younghwan Son, Minyeong Song, Youngwoo Park, Jaeduk Lee
  • Patent number: 10002806
    Abstract: The subject application relates to metrology targets with filling elements that reduce inaccuracies and maintain contrast. The present invention provides a metrology target and a method to design the metrology target. The metrology target comprises specified filling elements introduced into identified continuous regions in a given target design, wherein parameters of the introduced filling elements are determined by a trade-off between a contrast requirement and an inaccuracy requirement which is associated via production with the identified continuous regions. The method includes the steps of identifying continuous regions in a target design, and introducing specified filling elements into the identified continuous regions, wherein parameters of the introduced filling elements are determined by a trade-off between a contrast requirement and an inaccuracy requirement which is associated via production with the identifying continuous regions.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: June 19, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Nuriel Amir, Raviv Yohanan
  • Patent number: 9997475
    Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth Rodbell, Davood Shahrjerdi
  • Patent number: 9941471
    Abstract: A method for manufacturing a PCRAM memory includes forming in a first dielectric layer arranged on a substrate, which includes bottom electrodes, a first rectilinear trench opening onto the set of electrodes; depositing a first active layer in the first trench, such that the first active layer is in electrical contact with the electrodes; covering the first active layer with a second dielectric layer; etching, in the second and second dielectric layers and the first active layer, additional rectilinear trenches oriented perpendicularly to the first trench, to obtain a group of memory devices each including a portion of the first active layer in electrical contact with one of the electrodes; filling the additional trenches with a sacrificial dielectric material; performing an anisotropic etching of the sacrificial material to expose a side surface of each portion of the first active layer; and covering the side surface with a second active layer.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 10, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Gabriele Navarro
  • Patent number: 9941006
    Abstract: A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Arayashiki
  • Patent number: 9934850
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 3, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Hernan A. Castro
  • Patent number: 9893277
    Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Scott E. Sills, John K. Zahurak
  • Patent number: 9871076
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 16, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Xuan Anh Tran, Kiok Boone Elgin Quek
  • Patent number: 9812376
    Abstract: An electrically conductive element includes an electrically conductive material and a plurality of inclusions of a phase change material. The phase change material has a phase transition temperature Tc between 150° C. and 400° C. The inclusions are separated from each other and are embedded in the electrically conductive material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Stefan Woehlert, Michael Nelhiebel, Siegfried Roehl
  • Patent number: 9786512
    Abstract: Provided is an etching method for simultaneously etching first and second regions of a workpiece. The first region has a multilayered film configured by alternately laminating a silicon oxide film and a silicon nitride film and a second region has a silicon oxide film having a film thickness that is larger than that of the silicon oxide film in the first region. A mask is provided on the workpiece to at least partially expose each of the first and second regions. In the etching method, plasma of a first processing gas containing fluorocarbon gas, hydrofluorocarbon gas, and oxygen gas is generated within a processing container of a plasma processing apparatus. Subsequently, plasma of a second processing gas containing fluorocarbon gas, hydrofluorocarbon gas, oxygen gas, and a halogen-containing gas is generated within the processing container. Subsequently, plasma of a third processing gas containing oxygen gas is generated within the processing container.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: October 10, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yu Nagatomo, Ryuuu Ishita, Daisuke Tamura, Kousuke Koiwa
  • Patent number: 9779961
    Abstract: Disclosed is a method for etching a first region including a multi-layer film formed by providing silicon oxide films and silicon nitride films alternately, and a second region having a single silicon oxide film. The etching method includes: providing a processing target object including a mask provided on the first region and the second region within a processing container of a plasma processing apparatus; generating plasma of a first processing gas including a hydrofluorocarbon gas within the processing container that accommodates the processing target object; and generating plasma of a second processing gas including a fluorocarbon gas within the processing container that accommodates the processing target object. The step of generating the plasma of the first processing gas and the step of generating the plasma of the second processing gas are alternately repeated.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Saitoh, Yu Nagatomo, Hayato Hishinuma, Wataru Takayama, Sho Tominaga, Yuki Kaneko
  • Patent number: 9773841
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9767899
    Abstract: A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a disturb isolator circuit operatively coupled to the MEs to compensate for disturbances of a magnitude of a signal associated with a selected two-terminal resistive memory element in the array.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 19, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Chang Hua Siau
  • Patent number: 9741768
    Abstract: A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 22, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashot Melik-Martirosian, Juan Saenz
  • Patent number: 9735021
    Abstract: An etching method of etching a first region including a multilayered film, in which silicon oxide films and silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas, a hydrogen bromide gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 15, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masayuki Sawataishi, Tomonori Miwa
  • Patent number: 9721961
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi Okajima, Atsushi Oga, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Patent number: 9704923
    Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
  • Patent number: 9698049
    Abstract: A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 4, 2017
    Assignee: SK hynix Inc.
    Inventor: Kwang-Seok Oh
  • Patent number: 9659999
    Abstract: A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 23, 2017
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 9620564
    Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: April 11, 2017
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9614008
    Abstract: An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer which is formed over a substrate; a contact plug which is coupled with the substrate by passing through the inter-layer dielectric layer and has a protruding portion over the inter-layer dielectric layer; a first variable resistance pattern which is formed over the contact plug; and a protective layer which covers the first variable resistance pattern and a portion of sidewalls of the contact plug in such a manner that the sidewalls of the contact plug are exposed.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 4, 2017
    Assignee: SK hynix Inc.
    Inventors: Kwan-Woo Do, Ki-Seon Park
  • Patent number: 9613696
    Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 4, 2017
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Marco Pasotti, Marcella Carissimi, Vikas Rana