In Array Patents (Class 257/5)
  • Patent number: 11362107
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyun Han, Se Ho Lee, Hyangkeun Yoo, Jae Gil Lee
  • Patent number: 11322683
    Abstract: Technologies relating to crossbar array circuits with proton-based two-terminal volatile memristive devices are disclosed. An example apparatus includes: a first bottom conductive layer, a first switching oxide layer formed on the first bottom conductive layer, a first top conductive layer formed on the first switching oxide layer, an intermediate layer formed on the first top conductive layer, a second bottom conductive layer formed on the intermediate layer, a second oxide layer whose conductance can be modulated by H-dopant formed on the second bottom conductive layer; and a proton reservoir layer formed on the second oxide layer, wherein the second bottom conductive layer is H-doped.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 3, 2022
    Assignee: TetraMem, Inc.
    Inventor: Ning Ge
  • Patent number: 11283016
    Abstract: A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventor: Mario Allegra
  • Patent number: 11276704
    Abstract: A method for forming a semiconductor device is provided. In the disclosed method, a stack is formed on a working surface of a substrate. The stack has alternating first layers and second layers positioned over the substrate. A separation structure is formed in the stack that separates the stack into a first region and a second region, where the separation structure extends in a first direction of the substrate. The second layers in the second region are further replaced with insulating layers, and the first layers in the second region are doped with a dopant.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11276706
    Abstract: Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 15, 2022
    Inventors: Geunwon Lim, Yoonhwan Son, Junyoung Choi
  • Patent number: 11271041
    Abstract: A semiconductor memory includes a substrate including a first region in which a plurality of variable resistance elements are arranged, second and third regions on different sides of the first region, a plurality of first lines disposed over the substrate and extending across the first region and the second region, a plurality of second lines disposed over the first lines and extending across the first region and the third region. The variable resistance elements are positioned at intersections of the first lines and the second lines between the first lines and the second lines, a contact plug is disposed in the third region with an upper end coupled to the second line, and a resistive material layer is interposed between the second line and the variable resistance element in the first region but not between the second line and the contact plug in the third region.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Hwang-Yeon Kim
  • Patent number: 11271039
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Min-Seon Kang, Hyun-Seok Kang, Hyo-June Kim, Jae-Geun Oh, Su-Jin Chae
  • Patent number: 11271008
    Abstract: A semiconductor device includes: an alternating stack that is disposed over a lower structure and includes gate electrodes and dielectric layers which are staked alternately; a memory stack structure that includes a channel layer extending to penetrate through the alternating stack, and a memory layer surrounding the channel layer; a source contact layer in contact with a lower outer wall of the vertical channel layer and disposed between the lower structure and the alternating stack; a source contact plug spaced apart from the memory stack structure and extending to penetrate through the alternating stack; and a sealing spacer suitable for sealing the gate electrodes and disposed between the source contact plug and the gate electrodes. The sealing spacer has an etch resistance that is different from an etch resistance of the dielectric layers.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Jin-Ha Kim
  • Patent number: 11257866
    Abstract: A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 11258008
    Abstract: A nonvolatile memory device includes a semiconductor substrate, a memory array region including a plurality of word lines formed linearly along a plane having a height (h1), a plurality of linear bit lines formed linearly along a plane having a height (h2) in a direction intersecting the plurality of word lines, and a plurality of memory cells provided between an intersection portion of each of the plurality of word lines with the plurality of bit lines and each of the plurality of bit lines, and a peripheral circuit region including a plurality of linear electrodes formed linearly along a plane having a height (h1), a plurality of linear electrodes formed linearly along a plane having the height (h2) in a direction intersecting the plurality of linear electrodes, and an insulators provided at least between the plurality of linear electrodes and the plurality of linear electrodes.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 22, 2022
    Inventor: Toru Tanzawa
  • Patent number: 11257822
    Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani, Uygar E. Avci, Rajesh Kumar
  • Patent number: 11196001
    Abstract: Metal-assisted chemical etching is employed to form a three-dimensional (3D) resistive random access memory (ReRAM) in which the etching aspect ratio limit is extended and the top trench and bottom trench CD uniformity is improved. The 3D ReRAM includes a metal catalyst located between a bitline electrode and a selector device. Further, the 3D ReRAM includes vertically stacked and spaced apart replacement wordline electrodes that are located adjacent to the bitline electrode.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Kangguo Cheng, Wenyu Xu, Chen Zhang
  • Patent number: 11189790
    Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Sarah E. Atanasov, Kevin P. O'Brien, Robert L. Bristol
  • Patent number: 11133297
    Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 28, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kwang-Ho Kim, Masaaki Higashitani, Fumiaki Toyama, Akio Nishida
  • Patent number: 11133330
    Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
  • Patent number: 11101430
    Abstract: A phase-change storage element including, in a first portion, a stack of amorphous layers, the thickness of each layer in the stack being smaller than or equal to 5 nm.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 24, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Gabriele Navarro, Mathieu Bernard, Marie-Claire Cyrille, Chiara Sabbione
  • Patent number: 11075247
    Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anuj Gupta, Bipul C. Paul, Joe A. Versaggi
  • Patent number: 11069701
    Abstract: A semiconductor memory device includes a first conductive layer, second conductive layers extending in a first direction and stacked above the first conductive layer in a second direction, a third conductive layer between the first conductive layer and the second conductive layers, a memory pillar extending inside the second conductive layers in the second direction, a first insulating layer that isolates the second conductive layers in a third direction, and second insulating layers spaced from an end of the first insulating layer and extending in the third direction. The second insulating layers are spaced from an extension line of the first insulating layer that extends in the first direction. The first conductive layer includes a region that overlaps in the second direction a region where extension lines of the first and second insulating layers intersect, and the third conductive layer does not overlap this intersection region in the second direction.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosei Noda, Takeshi Murata, Mitsuhiko Noda
  • Patent number: 11049904
    Abstract: An RRAM structure includes a substrate. An RRAM is embedded in the substrate. The RRAM includes a bottom electrode, a metal oxide layer and a top electrode. A first doped region is embedded in the substrate and surrounds the bottom electrode. A transistor is disposed on the substrate and at one side of the RRAM. The transistor includes a gate structure on the substrate. A source is disposed in the substrate and at one side of the gate structure. A drain is disposed in the substrate and at another side of the gate structure. The first doped region contacts the drain.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 29, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Chin-Chun Huang, Yun-Pin Teng, Jinjian Ouyang, Wen Yi Tan
  • Patent number: 11043537
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Protruding tip portions are formed on each of the sacrificial material layers around the memory openings. A plurality of insulating spacers is formed within each memory opening between each vertically neighboring pair of tip portions of the sacrificial material layers. A phase change memory material and a vertical bit line are formed within each of the memory openings. The phase change memory material can be formed as a vertical stack of discrete annular phase change memory material portions, or can be formed as a continuous phase change memory material layer. Each of the sacrificial material layer can be replaced by an electrically conductive layer.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 22, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuji Takahashi, Masatoshi Nishikawa, Wei Kuo Shih
  • Patent number: 11011576
    Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jheng-Hong Jiang, Cheung Cheng, Chia-Wei Liu
  • Patent number: 11011544
    Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: May 18, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Patent number: 11004869
    Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 11, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
  • Patent number: 10998024
    Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chin Lin, Hung-Chang Yu
  • Patent number: 10950788
    Abstract: A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 16, 2021
    Assignee: 4DS MEMORY, LIMITED
    Inventor: Seshubabu Desu
  • Patent number: 10950664
    Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 10937833
    Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hui-Jung Kim, Kiseok Lee, Keunnam Kim, Yoosang Hwang
  • Patent number: 10930343
    Abstract: A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 23, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, Suhas Kumar, Xia Sheng
  • Patent number: 10916586
    Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 10916304
    Abstract: A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroyuki Hara
  • Patent number: 10892274
    Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Qian Tao, Haohao Yang, Jin Wen Dong, Jun Chen, Zhenyu Lu
  • Patent number: 10892410
    Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: January 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonghee Park, Jiho Park, Changyup Park, Dongho Ahn
  • Patent number: 10886333
    Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of source lines spaced apart from each other on a dielectric layer, forming a plurality of spacers on sides of the plurality of source lines, and forming a plurality of drain lines on the dielectric layer adjacent the plurality of source lines including the plurality of spacers formed thereon. In the method, a metal oxide layer is formed on the plurality of source lines and on the plurality of drain lines, and a plurality of gate lines are formed on the metal oxide layer. The plurality of gate lines are oriented perpendicular to the plurality of drain lines and the plurality of source lines.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan
  • Patent number: 10847578
    Abstract: A three-dimensional resistive memory is provided. The three-dimensional resistive memory includes a resistive switching pillar, an electrode pillar disposed within the resistive switching pillar, a stack of bit lines adjacent to the resistive switching pillar, a plurality of sidewall contacts between each of the bit lines and the resistive switching pillar, and a selector pillar extending through the stack of bit lines. The bit lines are separated vertically from each other by an insulating layer. The selector pillar contacts each of the sidewall contacts.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Windbond Electronics Corp.
    Inventor: Frederick Chen
  • Patent number: 10833015
    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 10, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10833124
    Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyo Seop Kim, Chang Woo Sun, Gyu Hwan Oh, Joon Kim, Joon Youn Hwang
  • Patent number: 10833269
    Abstract: A method is presented for constructing a three-dimensional (3D) stack phase change memory (PCM) device. The method includes forming a plurality of stack layers over a plurality of conductive lines, the plurality of conductive lines formed within trenches of an inter-layer dielectric (ILD), forming isolation trenches extending through the plurality of stack layers, etching the plurality of stack layers to define an opening, filling the opening with at least a phase change material, and constructing vias to the plurality of conductive lines.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Wang, Balasubramanian Pranatharthiharan, Injo Ok, Kevin W. Brew
  • Patent number: 10825516
    Abstract: Resistive change element cells sharing a selection device and resistive change element arrays including a plurality of resistive change element cells and a plurality of selection devices arranged in a group of at least two resistive change element cells sharing one selection device configuration are disclosed. According to some aspects of the present disclosure a group of resistive change element cells can be arranged on one level above a selection device. According to some aspects of the present disclosure a group of resistive change element cells can be arranged on multiple levels above a selection device.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Shiang-Meei Heh
  • Patent number: 10796756
    Abstract: Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin
  • Patent number: 10797234
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier Hinsinger
  • Patent number: 10790444
    Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Jen Tsai, Shih-Chang Liu
  • Patent number: 10777566
    Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 15, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10756267
    Abstract: A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 25, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Steve S. Chung, E-Ray Hsieh
  • Patent number: 10749528
    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventor: Sean Atsatt
  • Patent number: 10741582
    Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 11, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Patent number: 10734581
    Abstract: The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, D. V. Nirmal Ramaswamy
  • Patent number: 10734075
    Abstract: A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuki Inuzuka, Takaaki Nakazato
  • Patent number: 10700004
    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 30, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10658583
    Abstract: A memory device with crossbar array structure includes two sets of parallel bottom electrodes positioned on a substrate. The lower bottom electrodes are located at a lower position relative to higher bottom electrodes. The device includes a first set of corner tips of the lower bottom electrodes, and a second set of corner tips at a top of the higher bottom electrodes. The device also includes a set of parallel top electrodes intersecting the two sets of parallel bottom electrodes. A dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode. The device further includes one set of contacts at one end of an array that contacts the lower bottom electrodes and another set of contacts at the other end of the array that contacts the higher bottom electrodes.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Dexin Kong, Kangguo Cheng, Takashi Ando
  • Patent number: 10658428
    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Giorgio Servalli