In Array Patents (Class 257/5)
  • Patent number: 10916304
    Abstract: A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroyuki Hara
  • Patent number: 10916586
    Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 10892410
    Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: January 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonghee Park, Jiho Park, Changyup Park, Dongho Ahn
  • Patent number: 10892274
    Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Qian Tao, Haohao Yang, Jin Wen Dong, Jun Chen, Zhenyu Lu
  • Patent number: 10886333
    Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of source lines spaced apart from each other on a dielectric layer, forming a plurality of spacers on sides of the plurality of source lines, and forming a plurality of drain lines on the dielectric layer adjacent the plurality of source lines including the plurality of spacers formed thereon. In the method, a metal oxide layer is formed on the plurality of source lines and on the plurality of drain lines, and a plurality of gate lines are formed on the metal oxide layer. The plurality of gate lines are oriented perpendicular to the plurality of drain lines and the plurality of source lines.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan
  • Patent number: 10847578
    Abstract: A three-dimensional resistive memory is provided. The three-dimensional resistive memory includes a resistive switching pillar, an electrode pillar disposed within the resistive switching pillar, a stack of bit lines adjacent to the resistive switching pillar, a plurality of sidewall contacts between each of the bit lines and the resistive switching pillar, and a selector pillar extending through the stack of bit lines. The bit lines are separated vertically from each other by an insulating layer. The selector pillar contacts each of the sidewall contacts.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Windbond Electronics Corp.
    Inventor: Frederick Chen
  • Patent number: 10833124
    Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyo Seop Kim, Chang Woo Sun, Gyu Hwan Oh, Joon Kim, Joon Youn Hwang
  • Patent number: 10833015
    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 10, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10833269
    Abstract: A method is presented for constructing a three-dimensional (3D) stack phase change memory (PCM) device. The method includes forming a plurality of stack layers over a plurality of conductive lines, the plurality of conductive lines formed within trenches of an inter-layer dielectric (ILD), forming isolation trenches extending through the plurality of stack layers, etching the plurality of stack layers to define an opening, filling the opening with at least a phase change material, and constructing vias to the plurality of conductive lines.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Wang, Balasubramanian Pranatharthiharan, Injo Ok, Kevin W. Brew
  • Patent number: 10825516
    Abstract: Resistive change element cells sharing a selection device and resistive change element arrays including a plurality of resistive change element cells and a plurality of selection devices arranged in a group of at least two resistive change element cells sharing one selection device configuration are disclosed. According to some aspects of the present disclosure a group of resistive change element cells can be arranged on one level above a selection device. According to some aspects of the present disclosure a group of resistive change element cells can be arranged on multiple levels above a selection device.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Shiang-Meei Heh
  • Patent number: 10797234
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier Hinsinger
  • Patent number: 10796756
    Abstract: Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin
  • Patent number: 10790444
    Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Jen Tsai, Shih-Chang Liu
  • Patent number: 10777566
    Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 15, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10756267
    Abstract: A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 25, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Steve S. Chung, E-Ray Hsieh
  • Patent number: 10749528
    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventor: Sean Atsatt
  • Patent number: 10741582
    Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 11, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Patent number: 10734075
    Abstract: A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuki Inuzuka, Takaaki Nakazato
  • Patent number: 10734581
    Abstract: The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, D. V. Nirmal Ramaswamy
  • Patent number: 10700004
    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 30, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10658583
    Abstract: A memory device with crossbar array structure includes two sets of parallel bottom electrodes positioned on a substrate. The lower bottom electrodes are located at a lower position relative to higher bottom electrodes. The device includes a first set of corner tips of the lower bottom electrodes, and a second set of corner tips at a top of the higher bottom electrodes. The device also includes a set of parallel top electrodes intersecting the two sets of parallel bottom electrodes. A dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode. The device further includes one set of contacts at one end of an array that contacts the lower bottom electrodes and another set of contacts at the other end of the array that contacts the higher bottom electrodes.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Dexin Kong, Kangguo Cheng, Takashi Ando
  • Patent number: 10658428
    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Giorgio Servalli
  • Patent number: 10636810
    Abstract: Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 28, 2020
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yang-Kyu Choi, Jun-Young Park
  • Patent number: 10629607
    Abstract: A nonvolatile memory device may operate with a logic transistor, which includes a transistor gate formed of a material. The memory device includes a floating gate formed of the material, a first-type fin, and a second-type fin. The first-type fin includes a first-type channel, a first-type source, and a first-type drain. The first-type channel, the first-type source, and the first-type drain have a first conductivity type. The second-type fin includes a second-type channel, a second-type source, and a second-type drain. The second-type source and the second-type drain have the first conductivity type. The second-type channel has a second conductivity type opposite to the first conductivity type. The floating gate is positioned on the first-type channel and the second-type channel.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 21, 2020
    Inventors: David Liu, Ben Sheen
  • Patent number: 10600452
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Patent number: 10586794
    Abstract: The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 10, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mac D. Apodaca, Daniel Robert Shepard
  • Patent number: 10566529
    Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
  • Patent number: 10566277
    Abstract: Methods for designing semiconductor components, for fabricating semiconductor components, and corresponding semiconductor components are provided. In this case, capacitance structures are either coupled to a supply network or used for rectifying design violations.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventor: Andreas Kuesel
  • Patent number: 10541271
    Abstract: A voltage sensitive switching device is described having a superlattice-like cell structure comprising layers of ovonic materials, such as chalcogenide alloys. Memory cells can include the switching device, such as can be utilized in a cross-point memory.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 21, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Huai-Yu Cheng, Hsiang-Lan Lung, I-Ting Kuo
  • Patent number: 10535711
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 10529777
    Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that faces the first electrode, and a switch layer provided between the first electrode and the second electrode. The switch layer includes a chalcogen element. The switch device further includes a diffusion suppressing layer that is in contact with at least a portion of a surface of the switch layer, and suppresses diffusion of oxygen into the switch layer.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: January 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroaki Sei, Kazuhiro Ohba
  • Patent number: 10529778
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Unity Semiconductor Corporation
    Inventors: Lidia Vereen, Bruce L. Bateman, David A. Eggleston, Louis C. Parrillo
  • Patent number: 10514503
    Abstract: A method of fabricating a P-N junction in a semiconductor structure, e.g. silicon (Si) structure, is presented. The method may include several implantation steps performed at a single implantation angle with respect to the Si structure. In a first implantation step, a first dopant species is implanted over a first portion of the Si structure including a first edge of the Si structure. In a second implantation step, a second dopant species is implanted over a second portion of the Si structure including a second edge of the Si structure opposed to the first edge but excluding the first edge. The first portion and the second portion may overlap in a central portion of the Si structure between the first edge and the second edge, such that the second dopant species may be implanted below the first dopant species.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: December 24, 2019
    Assignee: The Governing Council of the University of Toronto
    Inventors: Joyce Kai See Poon, Zheng Yong, Wesley David Sacher
  • Patent number: 10510740
    Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10497753
    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli
  • Patent number: 10490667
    Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • Patent number: 10438655
    Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Jung Hyun Kwon, Yong Ju Kim, Do Sun Hong
  • Patent number: 10431596
    Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 1, 2019
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Patent number: 10403631
    Abstract: Embodiments of three-dimensional (3D) ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a 3D ferroelectric memory device includes a substrate and a plurality of ferroelectric memory cells each extending vertically above the substrate. Each of the ferroelectric memory cells includes a capacitor and a transistor electrically connected to the capacitor. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode. The transistor includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 3, 2019
    Assignee: Wuxi Petabyte Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Yushi Hu, Qian Tao
  • Patent number: 10403817
    Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul-ji Song, Sung-won Kim, Il-mok Park, Jong-chul Park, Ji-Hyun Jeong
  • Patent number: 10388870
    Abstract: Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 20, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Perumal Ratnam, Tanmay Kumar, Christopher Petti
  • Patent number: 10381304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Mark W. Kuemerle
  • Patent number: 10340447
    Abstract: A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Talia S. Gershon, Seyoung Kim, Dennis M. Newns, Teodor K. Todorov
  • Patent number: 10340283
    Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 2, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jung-Yi Guo, Chun-Min Cheng
  • Patent number: 10325653
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
  • Patent number: 10325958
    Abstract: A memory device includes a first interconnect extending in a first direction, semiconductor members extending in a second direction, a second interconnect provided between the semiconductor members and extending in a third direction, a first insulating film provided between the semiconductor member and the second interconnect, third interconnects extending in the second direction, fourth interconnects provided between the third interconnects and arranged along the second direction, a resistance change film provided between the third interconnect and the fourth interconnects, and a first film. The first film is provided between the second interconnect and the fourth interconnect, interposes between the semiconductor member and the resistance change film, and not interpose between the semiconductor member and the third interconnect connected to each other. A first end of the semiconductor member is connected to the first interconnect.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro Noda, Mutsumi Okajima
  • Patent number: 10269433
    Abstract: A memory device according to an embodiment includes word lines stacked in a third direction perpendicular to a first direction and a second direction; main bit lines including a first main bit line and extending in the second direction; transistors including first and second transistors of which the channel width is greater than the width of the main bit lines; sub-bit lines extending in the third direction and including a first sub-bit line electrically connected to the first main bit line, with the first transistor interposed therebetween, and a second sub-bit line electrically connected to the first main bit line, with the second transistor interposed therebetween, and being adjacent to the first sub-bit line, a line segment virtually connecting the first sub-bit line and the second sub-bit line intersecting the second direction; and a resistance-change layer provided between the word lines and the sub-bit lines.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mutsumi Okajima
  • Patent number: 10229920
    Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Qintao Zhang, Juntao Li, Geng Wang
  • Patent number: 10217799
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 10199568
    Abstract: According to one embodiment, a magnetic storage device includes a substrate, a dummy contact disposed on a top surface of the substrate, extending linearly in a direction substantially perpendicular to the top surface of the substrate, and floating electrically, and a magnetoresistive effect element included in a layer and insulated from the dummy contact, wherein the layer is disposed on the top surface of the dummy contact.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Nagamine, Young Min Eeh, Daisuke Watanabe, Kazuya Sawada, Toshihiko Nagase