Non-single Crystal, Or Recrystallized, Active Junction Adapted To Be Electrically Shorted (e.g., "anti-fuse" Element) Patents (Class 257/50)
  • Patent number: 10163916
    Abstract: A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N-well, an oxide layer deposited on the N-well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: December 25, 2018
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10163678
    Abstract: Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: December 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer Pendharkar, Guru Mathur, Takehito Tamura
  • Patent number: 10115729
    Abstract: An anti-fuse nonvolatile memory device includes an anti-fuse memory cell and a bipolar junction transistor. The anti-fuse, memory cell has a first terminal and a second terminal. The second terminal is coupled to a word line. The bipolar junction transistor has a collector terminal coupled to the first terminal of the anti-fuse, memory cell, a base terminal, and an emitter terminal coupled to a bit line.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 30, 2018
    Assignee: SK Hynix Inc.
    Inventor: Kwang II Choi
  • Patent number: 10032914
    Abstract: A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-? dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10032784
    Abstract: An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Synopsys, Inc.
    Inventors: Andrew E. Horch, Martin L. Niset, Ting-Jia Hu
  • Patent number: 9852982
    Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengwen Pei, Kangguo Cheng, Juntao Li, Geng Wang
  • Patent number: 9793001
    Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 17, 2017
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 9552890
    Abstract: The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: John M. Pigott, Randall C. Gray
  • Patent number: 9410921
    Abstract: A method for testing a CMOS transistor with an electrical testing unit, the CMOS transistor being formed in a semiconductor substrate of a semiconductor wafer. A plurality of CMOS transistors are formed on the semiconductor wafer and the electrical testing unit has a support plate and a metal layer formed on the support plate. The CMOS transistor having a first terminal contact, a second terminal contact and a third terminal contact, the second terminal contact configured as an electrically open control contact and in a process step the metal layer is positioned above the semiconductor wafer over the control contact and a potential difference between the first terminal contact and a third terminal contact is generated. The control contact is capacitively coupled by applying a drive potential to the metal layer, and the function of the CMOS transistor is tested by measuring an electrical variable dependent on the capacitive coupling.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: August 9, 2016
    Assignee: Micronas GmbH
    Inventor: Oliver Kawaletz
  • Patent number: 9406606
    Abstract: A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Hiroki Fujisawa
  • Patent number: 9385262
    Abstract: A method of manufacturing a semiconductor device provided with an interlayer insulating film formed on a semiconductor substrate, and a plurality of wiring layers formed on the interlayer insulating film. The method includes forming of a first wiring layer closest to the semiconductor substrate among the plurality of wiring layers, and forming of an alloy of a titanium layer and a metal layer by heating treatment. The forming of the first wiring layer includes: forming of a titanium layer on an interlayer insulating film; forming of a metal layer containing a metal capable of forming an alloy with titanium in the titanium layer; forming of an orientation layer on the metal layer; and forming of an aluminum layer on the orientation layer.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: July 5, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yukinobu Suzuki
  • Patent number: 9343674
    Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface of ruthenium or ruthenium silicide between the silicon material and the ruthenium material.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 9287165
    Abstract: A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: March 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Matthias Müller, Francisco Javier Santos Rodriguez, Daniel Schlögl
  • Patent number: 9257345
    Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: February 9, 2016
    Assignee: SK HYNIX INC.
    Inventor: Min Chul Sung
  • Patent number: 9142444
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 22, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Erwin Bacher, Andreas Behrendt, Joerg Ortner, Walter Rieger, Rudolf Zelsacher
  • Patent number: 9136471
    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto M. Meotto, Giorgio Servalli
  • Patent number: 9041202
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9013011
    Abstract: A staggered die MEMS package includes a substrate having a converter cavity formed therein. A converter electronic component is mounted within the converter cavity. Further, a MEMS electronic component is mounted to both the substrate and the converter electronic component in a staggered die arrangement. By staggering the MEMS electronic component directly on the converter electronic component instead of locating the MEMS electronic component in a side by side arrangement with the converter electronic component, the total package width of the staggered die MEMS package is minimized. Further, by locating the converter electronic component within the converter cavity and staggering the MEMS electronic component directly on the converter electronic component, the total package height, sometimes called Z-height, of the staggered die MEMS package is minimized.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 21, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Bob Shih-Wei Kuo, Brett Arnold Dunlap, Louis B. Troche, Jr., Ahmer Syed, Russell Shumway
  • Patent number: 9007838
    Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Zaitsu, Kosuke Tatsumura
  • Patent number: 9006844
    Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: April 14, 2015
    Assignee: DunAn Microstaq, Inc.
    Inventor: Parthiban Arunasalam
  • Patent number: 9006741
    Abstract: A memory device is provided, which includes a first conductive layer, a second conductive layer, and a memory layer interposed between the first conductive layer and the second conductive layer. The memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle. The nanoparticle includes a conductive material coated with an organic film. The first portion is in contact with the first conductive layer and the second conductive layer, and a side surface of the first portion is surrounded by the second portion.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kensuke Yoshizumi, Noriko Harima
  • Patent number: 8981524
    Abstract: An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film and an insulating film are alternately stacked over the first conductive layer, and a second conductive layer over the multilayer film. Voltage is applied between the first and second conductive layers and resistance of the multilayer film is decreased, whereby data is written to the memory element. When an insulating film having higher resistance than amorphous silicon is formed between the first and second conductive layers, current flowing through the antifuse at the time of writing is reduced.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Tajima, Hajime Tokunaga
  • Patent number: 8975701
    Abstract: An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Yeong Eui Hong
  • Patent number: 8969141
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventor: Laurentiu Vasiliu
  • Patent number: 8941110
    Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Chih-Chao Yang
  • Patent number: 8937357
    Abstract: According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: January 20, 2015
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen
  • Patent number: 8927312
    Abstract: A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Guy Cohen, Michael A. Guillorn, Effendi Leobandung, Fei Liu, Ghavam G. Shahidi
  • Patent number: 8884398
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • Patent number: 8878291
    Abstract: A semiconductor device includes a first buried gate structure in a peripheral circuit area of a semiconductor substrate, and a second gate structure formed on the semiconductor substrate. A gate insulating layer of a program transistor is thinly formed to be easily ruptured, and a gate insulating layer of a select transistor is thickly formed to improve reliability of the select transistor.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Yong Sun Jung
  • Patent number: 8877535
    Abstract: The present invention provides a vertical type sensor, including a substrate; a first electrode formed on the substrate; a sensing layer formed on the first electrode layer and reactive to a target substance, wherein the first electrode layer is interposed between the substrate and the sensing layer; and a second electrode layer formed on the sensing layer and having a plurality of openings, wherein the sensing layer is interposed between the first electrode layer and the second electrode layer, and the target substance contacts the sensing layer via the plurality of openings. The vertical type sensor of the present invention provides instant, sensitive and rapid detection.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: November 4, 2014
    Assignee: National Chiao Tung University
    Inventors: Hsiao-Wen Zan, Hsin-Fei Meng, Ming-Zhi Dai, Yu-Chiang Chao
  • Patent number: 8803282
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an access transistor, a read transistor, and an antifuse component coupled to the access transistor and the read transistor. In an embodiment, the read transistor can include a gate electrode, and the antifuse component can include a first electrode and a second electrode overlying the first electrode. The gate electrode and the first electrode can be parts of the same gate member. In another embodiment, the access transistor can include a gate electrode, and the antifuse component can include a first electrode, an antifuse dielectric layer, and a second electrode. The electronic device can further include a conductive member overlying the antifuse dielectric layer and the gate electrode of the access transistor, wherein the conductive member is configured to electrically float. Processes for making the same are also disclosed.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Thierry Coffi Herve Yao
  • Patent number: 8796687
    Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Mallanagouda Dyamanagouda Patil, Lili Tian, Natesan Venkataraman
  • Patent number: 8796739
    Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 5, 2014
    Assignee: Intersil Corporation
    Inventor: Michael D. Church
  • Patent number: 8759946
    Abstract: A semiconductor device which does not reduce writing property of a memory element and a method for manufacturing the same are proposed even in the case of forming a silicon film at a step portion formed by a surface of a substrate and a wiring formed over the substrate. The semiconductor device includes a plurality of the memory elements comprising a first electrode formed over a substrate having an insulating surface, sidewall insulating layer formed on side surface of the first electrode, a silicon film formed to cover the first electrode and the sidewall insulating layer, and a second electrode formed over the silicon film, and at least one of the first electrode and the second electrode is formed with a material being capable of being alloyed with the silicon film.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Tokunaga
  • Patent number: 8748859
    Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 10, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Christopher J Petti, Calvin K Li
  • Patent number: 8749020
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Shih-Hsun Hsu
  • Patent number: 8741697
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Thierry Coffi Herve Yao, Shizen Skip Liu
  • Patent number: 8735885
    Abstract: A memory device is provided, which includes a memory element including a first electrode, a second electrode, and a silicon layer disposed between the first electrode and the second electrode. The memory element is capable of being in a first state, a second state, and a third state. A first data is written to the memory element being in the first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the memory element being in the second state is obtained. A second data is written to the memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the memory element being in the third state is obtained.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Tokunaga
  • Patent number: 8704228
    Abstract: An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-song Ahn, Satoru Yamada, Young-jin Choi
  • Patent number: 8686419
    Abstract: A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Deepak C Sekar
  • Patent number: 8680524
    Abstract: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chi-sung Oh
  • Patent number: 8680514
    Abstract: An electric energy generator may include a semiconductor layer and a plurality of nanowires having piezoelectric characteristics. The electric energy generator may convert optical energy into electric energy if external light is applied and may generate piezoelectric energy if external pressure (e.g., sound or vibration) is applied.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8659020
    Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventors: Tadashi Kawashima, Masahiro Yoshikawa, Akira Inoue, Yoshiya Yoshida
  • Patent number: 8653595
    Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Adachi
  • Patent number: 8633567
    Abstract: A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: January 21, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8610245
    Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinsuke Tani, Toshiyuki Nakaiso
  • Patent number: 8610243
    Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Poppe, Andreas Kurz
  • Patent number: 8575719
    Abstract: Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 5, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, N. Johan Knall, S. Brad Herner
  • Patent number: 8569755
    Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Patent number: RE45517
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.