Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Abstract: A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.

Abstract: A semiconductor device includes a substrate including a first region and a second region adjacent to the first region, the first and the second regions being disposed in a first direction parallel to an upper surface of the substrate; an etch-stop layer disposed on the first region and the second region; a separation layer disposed on an upper portion of the etch-stop layer, the separation layer being disposed on the first region; a high-electron-mobility transistor (HEMT) element disposed on an upper portion of the separation layer in a second direction perpendicular to an upper surface of the substrate; a light-emitting element disposed on the second region between the substrate and the etch-stop layer; and a plurality of first insulating patterns covering side surfaces of the HEMT element, the plurality of first insulating patterns extending to the etch-stop layer.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.

Abstract: The present disclosure provides a method for manufacturing semiconductor device and a semiconductor device formed using same. The method includes: preparing a substrate; forming a pad oxide layer and a barrier layer on the substrate, the barrier layer is disposed on the pad oxide layer; forming a plurality of shallow trench isolation structures in the substrate to form multiple regions in the substrate; removing a part of the barrier layer to form a recess, the recess is set in any one of the multiple regions, and a region directly below the recess is defined as a high voltage device region; and forming a gate oxide layer in the recess, and removing the barrier layer. The method provided in the present disclosure simplifies the manufacturing process and reduces the production costs.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.

Abstract: An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.

Abstract: A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.

Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.

Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

Abstract: Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.

Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.

Abstract: A semiconductor device according to an embodiment is provided with a plurality of active barrier sections each of which is enclosed by a plurality of element isolation sections each of which is configured of a closed pattern. Namely, the plurality of active barrier sections are electrically isolated from each other.

Abstract: A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to deep trench isolation structures and methods of manufacture. The structure includes: at least one gate structure on a substrate; an interlevel dielectric material above the substrate; and a trench isolation structure extending into the substrate adjacent to the at least one gate structure and terminating in the interlevel dielectric material above the substrate.

Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

Abstract: A photoresist pattern is not formed in an outer circumferential region from an outer circumferential end of a semiconductor substrate up to 0.5 mm to 3.0 mm, in a process for patterning a silicon oxide film which will serve as a hard mask. A part of the silicon oxide film which is positioned in the outer circumferential region is removed, thereby exposing the semiconductor substrate, in a process for performing an etching process for patterning the silicon oxide film. In the process for performing the etching process for the semiconductor substrate with using the silicon oxide film as an etching mask, the surface of the semiconductor substrate of the outer circumferential region is lowered. Then, a step difference is formed in a position nearer to a chip formation region, in the semiconductor substrate.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type on a first electrode and a second semiconductor region of the first conductivity type on a central portion of the first semiconductor region. The second region has a carrier concentration less than a carrier concentration of the first region. A third semiconductor region of a second conductivity type is on the second semiconductor region. A first insulating portion covers a peripheral surface of the second semiconductor region and a peripheral surface of the third semiconductor region. A second insulating portion is spaced from the first insulating portion in a lateral direction. A void space is between the first and second insulating portions. A third insulating portion is on the third semiconductor region and spans and covers the void space. A second electrode is on the third semiconductor region and the third insulating portion.

Abstract: An electronic apparatus includes an electromagnetic radiation source structure and an electromagnetic radiation suppression structure. The electromagnetic radiation source structure is formed in at least one first semiconductor die. The electromagnetic radiation suppression structure is formed in a second semiconductor die, and is used for generating an inverse electromagnetic radiation against the electromagnetic radiation emission of the electromagnetic radiation source structure by sensing the electromagnetic radiation emission of the electromagnetic radiation source structure, to suppress the electromagnetic radiation emission of the electromagnetic radiation source structure from passing through the electromagnetic radiation suppression structure. Another electronic apparatus includes an electromagnetic radiation source structure and an electromagnetic radiation suppression structure. The electromagnetic radiation suppression structure is formed in a printed circuit board.

Abstract: A method of manufacturing a semiconductor device includes forming, over a semiconductor substrate comprising a first region and a second region, a patterned first film in which an upper face of a portion located over the first region is positioned at a lower height from the semiconductor substrate than an upper face of a portion located over the second region, forming, over the first film, a second film which is an insulating film, a portion of the second film penetrating the first film and being located inside a trench of the semiconductor substrate, and polishing the second film to remove a portion of the second film located over the first film. An occupancy of the trench in the first region is lower than an occupancy of the trench in the second region.

Abstract: A micro-electro-mechanical device includes a movable structure. The movable structure includes a test structure changing an electrical characteristic, if the movable structure is damaged. Further, a method for detecting damaging of a micro-electro-mechanical device includes detecting a change of an electrical characteristic of the electrical test structure of the movable structure. Further, the method includes indicating a deviation of the electrical characteristic from a predefined tolerable range.

Abstract: Radiation detectors having nanowires with charged, radiation-labile coatings configured to change the electrical properties of nanowires are provided. In one aspect, a radiation detection device is provided. The radiation detector device includes at least one nanowire having a radiation-labile coating with charged moieties on a surface thereof, wherein the radiation-labile coating is configured to degrade upon exposure to radiation such that the charged moieties are cleaved from the radiation-labile coating upon exposure to radiation and thereby affect a transconductance of the nanowire.

Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.

Abstract: Disclosed is an electronic module with high routing efficiency and other new possibilities in conductor design. The electronic module comprises a wiring layer (3), a component (1) having a surface with contact terminals (2) and first contact elements (6) that connect at least some of the contact terminals (2) to the wiring layer (3). The electronic module is provided with at least one conducting pattern (4) on the surface of the component (1) but spaced apart from the contact terminals (2). The electronic module further comprises a dielectric (5) and at least one second contact element (7) that connects the conducting pattern (4) to the wiring layer (3) through a portion of said dielectric (5). Methods of manufacturing such modules are also disclosed.

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract: A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region, and operates at a higher potential. A capacitor is on the connection region and transmits the second alternating current signal from the low-potential signal processing circuit to the high-potential signal processing circuit. The capacitor includes a low-potential electrode connected to the low-potential signal processing circuit, and a high-potential electrode connected to the high-potential signal processing circuit. First wiring layers of the low-potential electrode and second wiring layers of the high-potential electrode are capacitively coupled. Side wall surfaces of the first wiring layers and those of the second wiring layers are opposed to each other.

Abstract: In a semiconductor integrated circuit device including a digital circuit region in which a digital circuit is formed, and an analog circuit region in which an analog circuit is formed, the analog circuit region is separated into an active element region in which an active element of the analog circuit is formed, and a resistive and capacitive element region in which a resistor or a capacitor of the analog circuit is formed, the resistive and capacitive element region is arranged in a region adjacent to the digital circuit region, and the active element region is arranged in a region separated from the digital circuit region.

Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.

Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.

Abstract: Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature.

Abstract: In one embodiment, a method of forming a plug includes providing a base layer, providing an intermediate oxide layer above an upper surface of the base layer, providing an upper layer above an upper surface of the intermediate oxide layer, etching a trench including a first trench portion extending through the upper layer, a second trench portion extending through the oxide layer, and a third trench portion extending into the base layer, depositing a first material portion within the third trench portion, depositing a second material portion within the second trench portion, and depositing a third material portion within the first trench portion.

Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.

Abstract: Disclosed is an electronic module with high routing efficiency and other new possibilities in conductor design. The electronic module comprises a wiring layer (3), a component (1) having a surface with contact terminals (2) and first contact elements (6) that connect at least some of the contact terminals (2) to the wiring layer (3). The electronic module is provided with at least one conducting pattern (4) on the surface of the component (1) but spaced apart from the contact terminals (2). The electronic module further comprises a dielectric (5) and at least one second contact element (7) that connects the conducting pattern (4) to the wiring layer (3) through a portion of said dielectric (5). Methods of manufacturing such modules are also disclosed.

Abstract: Disclosed is an electronic module with high routing efficiency and other new possibilities in conductor design. The electronic module comprises a wiring layer (3), a component (1) having a surface with contact terminals (2) and first contact elements (6) that connect at least some of the contact terminals (2) to the wiring layer (3). The electronic module is provided with at least one conducting pattern (4) on the surface of the component (1) but spaced apart from the contact terminals (2). The electronic module further comprises a dielectric (5) and at least one second contact element (7) that connects the conducting pattern (4) to the wiring layer (3) through a portion of said dielectric (5). Methods of manufacturing such modules are also disclosed.