Including High Voltage Or High Power Devices Isolated From Low Voltage Or Low Power Devices In The Same Integrated Circuit Patents (Class 257/500)
  • Patent number: 10991797
    Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Peng Xu, Chun Wing Yeung
  • Patent number: 10930776
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu
  • Patent number: 10903374
    Abstract: A semiconductor device includes a first JTE region formed around an active portion, a second JTE region formed around the first JTE region, and a third JTE region formed around the second JTE region. The first, second, and third JTE regions are doped with an impurity of a second conductivity type different from a first conductivity type. A concentration ratio R21 “(concentration of impurity in second JTE region)/(concentration of impurity in first JTE region)” and a concentration ratio R32 “(concentration of impurity in third JTE region)/(concentration of impurity in second JTE region)” are 0.50 or greater and 0.65 or less. A width W1 of the first JTE region, a width W2 of the second JTE region, and a width W3 of the third JTE region are 130 ?m or greater and 190 ?m or less.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 26, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hidenori Kitai, Hiromu Shiomi, Kenji Fukuda
  • Patent number: 10872952
    Abstract: A MOSFET according to the present invention includes a semiconductor base substrate having a super junction structure. A gate electrode is on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein in a state where a total amount of dopant in an n-type column region differs from a total amount of dopant in a p-type column region, assuming a depth position where an average positive charge density ?(x) becomes 0 as Xm?, assuming a deepest depth position of the surface of the depletion layer on the first main surface side as X0?, assuming a depth position where the reference average positive charge density ?0(x) becomes 0 as Xm, and assuming a deepest depth position of the depletion layer on the first main surface side as X0, a relationship of |X0?X0?|<|Xm?Xm?| is satisfied.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 22, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada
  • Patent number: 10854600
    Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 1, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
  • Patent number: 10811497
    Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: October 20, 2020
    Assignee: Silanna Asia Pte Ltd
    Inventors: Vadim Kushner, Nima Beikae
  • Patent number: 10778217
    Abstract: An electronic switching circuit, in particular a solid state relay, provides bidirectional electronic power switching. The circuit can be connected to a load and an electrical voltage source. It includes two field effect transistors and a control circuit. The control circuit is conductively connected to the respective gate terminal of the field effect transistors. The field effect transistors are connected in an anti-serial configuration.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 15, 2020
    Inventor: Thomas Kliem
  • Patent number: 10714375
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10636740
    Abstract: A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 28, 2020
    Assignees: FUJI ELECTRIC CO., LTD., KOJIN CO., LTD.
    Inventors: Motohito Hori, Yuki Inaba, Yoshinari Ikeda, Tetsuya Sunago, Michihiro Inaba
  • Patent number: 10636900
    Abstract: A power semiconductor transistor includes an electrically conductive contact structure including a plurality of contacts. A first one of the contacts is electrically connected to both a first load terminal and a first zone of a doped semiconductor structure. A second one of the contacts is electrically coupled to one of the first load terminal and a control electrode. The second contact laterally overlaps with both a second zone of the doped semiconductor structure, and a gap is formed between two adjacent field plates. The second zone of the doped semiconductor structure terminates in a section laterally overlapping with the gap.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Viktoryia Uhnevionak, Philip Christoph Brandt, Frank Hille, Alexandra Ludsteck-Pechloff, Frank Dieter Pfirsch
  • Patent number: 10573671
    Abstract: A flexible organic light emitting diode display and manufacturing method thereof are provided. The method includes: performing a first patterning process on an amorphous silicon film; performing a crystallization treatment on the amorphous silicon film which has been processed by the first patterning process to form an oriented crystalline polycrystalline silicon film; performing a second patterning process on the polycrystalline silicon film to form a channel; and sequentially forming a gate, a source, a drain, an OLED display layer, and a packaging layer over the channel.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: February 25, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Wei Wang
  • Patent number: 10559553
    Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 11, 2020
    Assignee: General Electric Company
    Inventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
  • Patent number: 10541299
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 21, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10529568
    Abstract: Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Pramit Manna, Rui Cheng, Abhijit Basu Mallick
  • Patent number: 10497694
    Abstract: A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Guenther Kolmeder
  • Patent number: 10437550
    Abstract: The invention relates to a device for controlling an audio output for a motor vehicle. The device comprises the following: an output summation device for controlling a playback of generated audio output signals on the basis of first audio signals and second audio signals; a first processor device which has at least one processor core and which is designed to generate the first audio signals for a first motor vehicle component group assigned to the first processor device; and a second processor device which has at least one processor core and which is designed to generate second audio signals for a second motor vehicle component group assigned to the second processor device and to actuate the output summation device.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 8, 2019
    Assignee: Continental Automotive GmbH
    Inventors: Holger Braun, Abdul Khaliq
  • Patent number: 10389240
    Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 20, 2019
    Assignee: EMPOWER SEMICONDUCTOR
    Inventor: Timothy Alan Phillips
  • Patent number: 10381342
    Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yang Xiu, Aravind C Appaswamy, Akram Salman, Mariano Dissegna
  • Patent number: 10319809
    Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
  • Patent number: 10104765
    Abstract: A printed wiring board includes a digital circuit, an analog circuit, and a power supply path that is disposed on an insulating layer between the digital circuit and the analog circuit. EBG unit cells are disposed on a boundary between the digital circuit and the analog circuit one dimensionally or two dimensionally and periodically, and an interdigital electrode is formed. A magnetic body film is formed over the printed wiring board, partially formed on the EBG unit cells, or formed avoiding the EBG unit cells.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 16, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Yoshitaka Toyota, Kengo Iokibe, Yuki Yamashita, Masanori Naito, Toshiyuki Kaneko, Kiyohiko Kaiya, Toshihisa Uehara, Koichi Kondo
  • Patent number: 10062778
    Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher tha
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 28, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Naoki Izumi, Tomoyasu Sada
  • Patent number: 10050553
    Abstract: A rectifier circuit is described, which includes a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, an electronic circuit which includes at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor operated in the avalanche mode corresponding to the clamping voltage between the cathode terminal and the anode terminal of the rectifier circuit. In addition, a method is provided for operating a rectifier circuit which contains a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor being selected in accordance with the clamping voltage between the cathode terminal and the anode terminal, and the MOSFET transistor being operated in the avalanche mode.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 14, 2018
    Assignees: Robert Bosch GmbH, SEG Automotive Germany GmbH
    Inventors: Markus Baur, Alfred Goerlach
  • Patent number: 10014369
    Abstract: A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 3, 2018
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Sung-Nien Tang, Ho-Tai Chen, Hsiu-Wen Hsu
  • Patent number: 9997511
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 12, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9997621
    Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 12, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Hitoshi Matsuura, Yuya Abiko
  • Patent number: 9966406
    Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 9881927
    Abstract: CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Chia-Hong Jan, Walid M. Hafez, Joodong Park
  • Patent number: 9876106
    Abstract: A trench power transistor and a manufacturing method thereof are provided. The trench power transistor includes a substrate, an epitaxial layer, a trench gate structure, a body region, and a source region. The epitaxial layer disposed on the substrate has a trench formed therein. The trench gate structure disposed in the trench includes a bottom dielectric structure, a gate dielectric layer, and a gate. The bottom dielectric structure formed in a lower portion of the trench includes an insulating layer formed along a first inner wall of the lower portion of the trench defining a groove, and a non-conductive structure formed in the groove. The gate dielectric layer is formed along a second inner wall of an upper portion of the trench, and the gate is formed in the trench and connects the gate dielectric layer. The body region and the source region are formed in the epitaxial layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 23, 2018
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 9831231
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9812489
    Abstract: An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500° C. and 550° C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 7, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Daniel Tekleab
  • Patent number: 9754950
    Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Dong Hwan Lee, Min Gyu Koo, Hyun Heo
  • Patent number: 9748343
    Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface inclined with respect to a {000-1} face at an angle of 0° to 10° or a surface a normal line direction of which is inclined with respect to a <000-1> direction at an angle of 80° to 90°, a gate electrode, an insulating layer at least a part of which is provided between the surface and the gate electrode, and a region, at least apart of which is provided between the surface and the insulating layer, including a bond between carbon and carbon.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 29, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 9741711
    Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 22, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Woochul Jeon, Jason McDonald
  • Patent number: 9698773
    Abstract: The present invention is provided to easily manufacture an IPD as any of a high-side switch and a low-side switch. A level shifting circuit is coupled to an input terminal, a first terminal, and a grounding terminal. Drive power of the level shifting circuit is supplied from the first terminal. An output signal of the level shifting circuit is input to a driver circuit. The driver circuit is coupled to the first terminal and a second terminal. Drive power of the driver circuit is supplied from the first terminal. A transistor has a gate electrode coupled to the driver circuit, a source coupled to the second terminal, and a drain coupled to a third terminal.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: July 4, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Yanagigawa
  • Patent number: 9691895
    Abstract: A device includes a plurality of isolation regions formed in a substrate, wherein a top surface of a first isolation region is lower than a top surface of the substrate and a second isolation region has a first portion in a high voltage region and a second portion in a low voltage region, a first gate electrode layer over the high voltage region, a second gate electrode layer over the second isolation region and a third gate electrode layer over the low voltage region, wherein a bottom surface of the first gate electrode layer is higher than a bottom surface of the third gate electrode layer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huei-Ru Liu, Chien-Chih Chou, Kong-Beng Thei
  • Patent number: 9653453
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 16, 2017
    Assignee: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
  • Patent number: 9614033
    Abstract: An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact area is at a second side of the semiconductor body opposite to the first side. A control terminal contact area is at the second side of the semiconductor body. An isolation structure extends through the semiconductor body between the first and second sides. The isolation structure electrically isolates a first part of the semiconductor body from a second part of the semiconductor body. A first thickness of the first part of the semiconductor body is smaller than a second thickness of the second part of the semiconductor body.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Till Schloesser
  • Patent number: 9530837
    Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 9520463
    Abstract: A super junction semiconductor device includes a super junction structure and a channel stopper structure. The super junction structure includes first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. The channel stopper structure includes a doped semiconductor region electrically coupled to a field plate. The second semiconductor regions extend along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 13, 2016
    Assignee: Infineon Technologies Austra AG
    Inventor: Hans Weber
  • Patent number: 9502441
    Abstract: An array substrate with connecting leads and a manufacturing method thereof are provided. The array substrate includes a substrate; a plurality of signal lines formed of a metal layer, which are disconnected at a cut zone of the substrate; a plurality of connecting leads disposed in an adjacent layer of the signal lines, which correspond to locations of the signal lines where they are disconnected, and directly contact with the signal lines; wherein, two ends of each of the signal lines in its disconnected position are electrically joined by the connecting leads, and the signal lines include gate lines, the connecting leads include first leads; wherein, the first leads are formed on the substrate, and the gate lines are located in an upper level than the first leads.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: November 22, 2016
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Haichen Hu, Yusheng Xi, Jiarong Liu
  • Patent number: 9496345
    Abstract: The present invention provides a semiconductor structure which includes at least a p-type silicon carbide single crystal layer having an ?-type crystal structure, containing aluminum at impurity concentration of 1×1019 cm?3 or higher, and having thickness of 50 ?m or greater. Further provided is a method for producing the semiconductor structure of the present invention which method includes at least epitaxial growth step of introducing silicon carbide source and aluminum source and epitaxially growing p-type silicon carbide single crystal layer over a base layer made of silicon carbide single crystal having ?-type crystal structure, wherein the epitaxial growth step is performed at temperature conditions of from 1,500° C. to 1,700° C., and pressure conditions of from 5×103 Pa to 25×103 Pa.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 15, 2016
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY
    Inventors: Kazutoshi Kojima, Shiyang Ji, Tetsuya Miyazawa, Hidekazu Tsuchida, Koji Nakayama, Tetsuro Hemmi, Katsunori Asano
  • Patent number: 9478539
    Abstract: An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound semiconductor stack structure; a first insulating film which is formed on the element region and is not formed on the element isolation structure; a second insulating film which is formed on at least the element isolation structure and is higher in hydrogen content than the first insulating film; and a gate electrode which is formed on the element region of the compound semiconductor stack structure via the second insulating film.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: October 25, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Toshihide Kikkawa
  • Patent number: 9466371
    Abstract: A transistor is described including a fly-over conductor. The transistor has a gate, a channel and a source/drain terminal. The fly-over conductor is disposed over the source/drain terminal. A circuit is connected to the fly-over conductor to apply a bias voltage tending to offset effects on the transistor of charge trapped in insulating material. A word line driver can include a transistor with a fly-over conductor.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: October 11, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi-Peng Chang, Yin-Jen Chen
  • Patent number: 9406708
    Abstract: The present invention provides an image sensor device including a substrate, a channel formed in the substrate, a photoelectric transfer region formed in the substrate located at one side of the channel, a voltage transfer region formed in the substrate located at the other side of the channel, a first gate dielectric layer formed on the substrate, a second gate dielectric layer formed on the substrate, wherein the first gate dielectric layer and the second gate dielectric layer have a joint above the channel, and the thickness of the first gate dielectric layer is thicker than that of the second gate dielectric layer, and a gate formed on the first gate dielectric layer and the second gate a is dielectric layer. The present invention also provides a method for fabricating the image sensor device.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: August 2, 2016
    Assignee: SILICON OPTRONICS, INC.
    Inventor: Yu-Yuan Yao
  • Patent number: 9373560
    Abstract: A drive circuit device includes a circuit board having a multilayer structure, which includes first to fourth circuit conductor layers, and first to third insulating layers; and heat sinks that dissipate heat of the circuit board to an outside. An upper FET state is embedded in the first insulating layer, and a lower FET state is embedded in the second insulating layer. The upper FET and the lower FET are disposed so that a region in which the upper FET is positioned and a region in which the lower FET is positioned overlap each other in a stacking direction. A lead-out portion is formed at a second circuit pattern of the circuit conductor layer, the lead-out portion extending from the circuit board in a direction orthogonal to the stacking direction, and being connected to the heat sinks so that heat is transferred to the heat sinks.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 21, 2016
    Assignee: JTEKT CORPORATION
    Inventor: Nobuhiro Uchida
  • Patent number: 9312371
    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Patent number: 9299833
    Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher tha
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: March 29, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Naoki Izumi, Tomoyasu Sada
  • Patent number: 9287371
    Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 15, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Ana Villamor, Piet Vanmeerbeek, Jaume Roig-Guitart, Filip Bogman
  • Patent number: 9281362
    Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ja-Young Lee, Se-myeong Jang
  • Patent number: 9224732
    Abstract: A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Chia-Chin Shen, Eric Huang, Fu Chin Yang, Chun Lin Tsai, Hsiao-Chin Tuan