Including High Voltage Or High Power Devices Isolated From Low Voltage Or Low Power Devices In The Same Integrated Circuit Patents (Class 257/500)
  • Patent number: 11889768
    Abstract: The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 30, 2024
    Assignee: FERDINAND-BRAUN-INSTITUT GGMBH, LEIBNIZ-INSTITUT FUR HÖCHSTFREQUENZTECHNIK
    Inventors: Konstantin Osipov, Hans-Joachim Wuerfl
  • Patent number: 11880032
    Abstract: Embodiments of the disclosure provide a micromachined mirror assembly. The micromachined mirror assembly includes a micro mirror configured to tilt around an axis and a first and a second torsion beam each having a first and a second end. The second end of the first torsion beam and the second end of the second torsion beam are mechanically coupled to the micro mirror along the axis. The micromachined mirror assembly also includes a first DC voltage applied to the first end of the first torsion beam and a second DC voltage, different from the first DC voltage, is applied to the first end of the second torsion beam.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: January 23, 2024
    Assignee: BEIJING VOYAGER TECHNOLOGY CO., LTD.
    Inventors: Sae Won Lee, Youmin Wang, Qin Zhou
  • Patent number: 11874457
    Abstract: A method for projecting an image comprising providing a scanning mirror having a resonance frequency which is unequal to a target operating frequency (aka “scanning frequency”) at which the mirror is to operate; and/or providing logic and an actuator e.g. motor; and/or using the scanning mirror to project at least one image, including repeatedly using the logic to measure the mirror's operating frequency and to control the actuator to apply at least one force, to the mirror, which causes the mirror's instantaneous operating frequency to equal the target operating frequency.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: January 16, 2024
    Assignee: MARADIN LTD.
    Inventors: Matan Naftali, Ran Gabai, Gil Cahana, Menashe Yehiel
  • Patent number: 11855136
    Abstract: A super junction semiconductor device includes a substrate of a first conductive type, an epitaxial layer disposed on the substrate, a plurality of pillars extending in a vertical direction and each being alternately arranged within the epitaxial layer, gate structures disposed on the epitaxial layer in the active region, a reverse recovery layer of a second conductive type, the reverse recovery layer disposed on both the pillars and the epitaxial layer and in the transition region to distribute a reverse recovery current, and at least one high concentration region surrounding an upper portion of at least one of the pillars in the peripheral region, the high concentration region having a horizontal width greater than that of one of the pillars provided in the transition region. Thus, a breakdown voltage may be inhibited from decreasing in the peripheral region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 26, 2023
    Assignee: DB HITEK CO., LTD.
    Inventors: Ji Eun Lee, Jae Hyun Kim
  • Patent number: 11848378
    Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 19, 2023
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Ditto Adnan, Maurizio Gabriele Castorina, Voon Cheng Ngwan, Fadhillawati Tahir
  • Patent number: 11774303
    Abstract: An accelerator is an automobile accelerator. The accelerator includes a sensor configured to detect a force to press the accelerator. The sensor includes a flexible substrate and a resistor formed of a film containing Cr, CrN, and Cr2N, on or above the substrate. The sensor is configured to detect the force to press the accelerator as a change in a resistance value of the resistor.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 3, 2023
    Assignee: MINEBEA MITSUMI Inc.
    Inventors: Atsushi Kitamura, Shigeyuki Adachi, Toshiaki Asakawa, Eiji Misaizu
  • Patent number: 11742349
    Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Patent number: 11737368
    Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Daniel Ouellette, Christopher Wiegand, Justin Brockman, Tofizur Rahman, Oleg Golonzka, Angeline Smith, Andrew Smith, James Pellegren, Michael Robinson, Huiying Liu
  • Patent number: 11610028
    Abstract: A method for designing an optical scanning mirror is provided. The method may include receiving, by a communication interface, a set of design parameters of the scanning mirror. The method may also include simulating scanning mirror oscillation, by at least one processor, based on the set of design parameters using a computer model. In certain aspects, the computer model may include a lookup table that correlates electrostatic force applied to a sample scanning mirror and angular displacement in the sample scanning mirror caused by the electrostatic force. The method may further include generating, by the at least one processor, mirror oscillation data as an output of the computer model for designing the scanning mirror. The mirror oscillation data may include a correlation of drive frequency, angular displacement, and time.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 21, 2023
    Assignee: BEIJING VOYAGER TECHNOLOGY CO., LTD.
    Inventors: Youmin Wang, Yufeng Wang, Gary Li
  • Patent number: 11502036
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirokazu Sayama, Fumihiko Hayashi, Junjiro Sakai
  • Patent number: 11417739
    Abstract: Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11355628
    Abstract: A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge.
    Type: Grant
    Filed: November 17, 2019
    Date of Patent: June 7, 2022
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 11300610
    Abstract: An integrated circuit, a crack status detector and a crack status detection method are provided. The crack status detector includes a detection ring, multiple switches, and a current measuring circuit. The detection ring is formed by multiple conductive wire segments coupled in series. The detection ring is disposed adjacent to a side of at least one guard ring in the integrated circuit. The detection ring has a first endpoint and a second endpoint to respectively receive a first reference voltage and a second reference voltage. Each of the switches is disposed between two adjacent conductive wire segments. The switches are respectively turned on or cut off according to multiple control signals. The current measuring circuit transmits the control signals and measures a current on the detection ring according to a turned-on or cut-off status of each of the switches, so as to detect a crack status of the integrated circuit.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Tung Tang
  • Patent number: 11302692
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Patent number: 11289484
    Abstract: A semiconductor device is provided. The semiconductor device includes an n-doped field effect transistor (nFET) section, a p-doped field effect transistor (pFET) section and an insulator pillar. The nFET section includes nFET nanosheets and nFET source or drain (S/D) regions partially surrounding the nFET nanosheets. The pFET section includes pFET nanosheets and pFET S/D regions partially surrounding the pFET nanosheets. The insulator pillar is interposed between the nFET S/D regions and the pFET S/D regions to form a fork-sheet structure with the nFET nanosheets and the pFET nanosheets.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Ruilong Xie, Xin Miao, Alexander Reznicek
  • Patent number: 11227945
    Abstract: A transistor device includes at least one transistor cell which includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode. A portion of the semiconductor body is arranged between the field electrode trench and the first surface of the semiconductor body. The portion of the semiconductor body that is arranged between the field electrode trench and the first surface comprises the body region. The body region directly contacts the upper surface of the field electrode dielectric.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: January 18, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler
  • Patent number: 11195932
    Abstract: In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Prashant Majhi, Ravi Pillarisetty, Elijah V. Karpov
  • Patent number: 11195906
    Abstract: A semiconductor device includes a semiconductor substrate that includes an element region and a peripheral withstand voltage region. An insulating protection film is provided above the peripheral withstand voltage region. The peripheral withstand voltage region includes a plurality of guard ring regions of p-type in direct contact with the insulating protection film and a drift region of n-type separating the guard ring regions from each other. Each guard ring region includes a guard ring low concentration region being in direct contact with the insulating protection film and a guard ring high concentration region having a p-type impurity concentration equal to or more than ten times as high as that in the corresponding guard ring low concentration region. Each guard ring high concentration region is provided under the corresponding guard ring low concentration region, and separated from the insulating protection film by the corresponding guard ring low concentration region.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 7, 2021
    Assignee: Denso Corporation
    Inventor: Takashi Okawa
  • Patent number: 11183495
    Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 23, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sun-hak Lee, Yong Zhong Hu, Hye-mi Kim
  • Patent number: 11107917
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first doped well, a second doped well, a mixed doped well, and a gate structure. The first, the second, and the mixed doped wells are disposed in the semiconductor substrate. At least a part of the first doped well and at least a part of the second doped well are located at two opposites sides of the gate structure in a horizontal direction respectively. The mixed doped well are located between the first doped well and the second doped well. The first and the second doped well include a first conductivity type dopant and a second conductivity type dopant respectively. The mixed doped well includes a mixed dopant. A part of the mixed dopant is identical to the first conductivity type dopant, and another part of the mixed dopant is identical to the second conductivity type dopant.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: August 31, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: I-Jhen Hsu, Chih-Hua Liu, Kai-Yi Huang, Ta-Hsun Yeh
  • Patent number: 10991797
    Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Peng Xu, Chun Wing Yeung
  • Patent number: 10930776
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu
  • Patent number: 10903374
    Abstract: A semiconductor device includes a first JTE region formed around an active portion, a second JTE region formed around the first JTE region, and a third JTE region formed around the second JTE region. The first, second, and third JTE regions are doped with an impurity of a second conductivity type different from a first conductivity type. A concentration ratio R21 “(concentration of impurity in second JTE region)/(concentration of impurity in first JTE region)” and a concentration ratio R32 “(concentration of impurity in third JTE region)/(concentration of impurity in second JTE region)” are 0.50 or greater and 0.65 or less. A width W1 of the first JTE region, a width W2 of the second JTE region, and a width W3 of the third JTE region are 130 ?m or greater and 190 ?m or less.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 26, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hidenori Kitai, Hiromu Shiomi, Kenji Fukuda
  • Patent number: 10872952
    Abstract: A MOSFET according to the present invention includes a semiconductor base substrate having a super junction structure. A gate electrode is on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein in a state where a total amount of dopant in an n-type column region differs from a total amount of dopant in a p-type column region, assuming a depth position where an average positive charge density ?(x) becomes 0 as Xm?, assuming a deepest depth position of the surface of the depletion layer on the first main surface side as X0?, assuming a depth position where the reference average positive charge density ?0(x) becomes 0 as Xm, and assuming a deepest depth position of the depletion layer on the first main surface side as X0, a relationship of |X0?X0?|<|Xm?Xm?| is satisfied.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 22, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada
  • Patent number: 10854600
    Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 1, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
  • Patent number: 10811497
    Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: October 20, 2020
    Assignee: Silanna Asia Pte Ltd
    Inventors: Vadim Kushner, Nima Beikae
  • Patent number: 10778217
    Abstract: An electronic switching circuit, in particular a solid state relay, provides bidirectional electronic power switching. The circuit can be connected to a load and an electrical voltage source. It includes two field effect transistors and a control circuit. The control circuit is conductively connected to the respective gate terminal of the field effect transistors. The field effect transistors are connected in an anti-serial configuration.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 15, 2020
    Inventor: Thomas Kliem
  • Patent number: 10714375
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10636900
    Abstract: A power semiconductor transistor includes an electrically conductive contact structure including a plurality of contacts. A first one of the contacts is electrically connected to both a first load terminal and a first zone of a doped semiconductor structure. A second one of the contacts is electrically coupled to one of the first load terminal and a control electrode. The second contact laterally overlaps with both a second zone of the doped semiconductor structure, and a gap is formed between two adjacent field plates. The second zone of the doped semiconductor structure terminates in a section laterally overlapping with the gap.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Viktoryia Uhnevionak, Philip Christoph Brandt, Frank Hille, Alexandra Ludsteck-Pechloff, Frank Dieter Pfirsch
  • Patent number: 10636740
    Abstract: A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 28, 2020
    Assignees: FUJI ELECTRIC CO., LTD., KOJIN CO., LTD.
    Inventors: Motohito Hori, Yuki Inaba, Yoshinari Ikeda, Tetsuya Sunago, Michihiro Inaba
  • Patent number: 10573671
    Abstract: A flexible organic light emitting diode display and manufacturing method thereof are provided. The method includes: performing a first patterning process on an amorphous silicon film; performing a crystallization treatment on the amorphous silicon film which has been processed by the first patterning process to form an oriented crystalline polycrystalline silicon film; performing a second patterning process on the polycrystalline silicon film to form a channel; and sequentially forming a gate, a source, a drain, an OLED display layer, and a packaging layer over the channel.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: February 25, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Wei Wang
  • Patent number: 10559553
    Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 11, 2020
    Assignee: General Electric Company
    Inventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
  • Patent number: 10541299
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 21, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10529568
    Abstract: Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Pramit Manna, Rui Cheng, Abhijit Basu Mallick
  • Patent number: 10497694
    Abstract: A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Guenther Kolmeder
  • Patent number: 10437550
    Abstract: The invention relates to a device for controlling an audio output for a motor vehicle. The device comprises the following: an output summation device for controlling a playback of generated audio output signals on the basis of first audio signals and second audio signals; a first processor device which has at least one processor core and which is designed to generate the first audio signals for a first motor vehicle component group assigned to the first processor device; and a second processor device which has at least one processor core and which is designed to generate second audio signals for a second motor vehicle component group assigned to the second processor device and to actuate the output summation device.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 8, 2019
    Assignee: Continental Automotive GmbH
    Inventors: Holger Braun, Abdul Khaliq
  • Patent number: 10389240
    Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 20, 2019
    Assignee: EMPOWER SEMICONDUCTOR
    Inventor: Timothy Alan Phillips
  • Patent number: 10381342
    Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yang Xiu, Aravind C Appaswamy, Akram Salman, Mariano Dissegna
  • Patent number: 10319809
    Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
  • Patent number: 10104765
    Abstract: A printed wiring board includes a digital circuit, an analog circuit, and a power supply path that is disposed on an insulating layer between the digital circuit and the analog circuit. EBG unit cells are disposed on a boundary between the digital circuit and the analog circuit one dimensionally or two dimensionally and periodically, and an interdigital electrode is formed. A magnetic body film is formed over the printed wiring board, partially formed on the EBG unit cells, or formed avoiding the EBG unit cells.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 16, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Yoshitaka Toyota, Kengo Iokibe, Yuki Yamashita, Masanori Naito, Toshiyuki Kaneko, Kiyohiko Kaiya, Toshihisa Uehara, Koichi Kondo
  • Patent number: 10062778
    Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher tha
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 28, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Naoki Izumi, Tomoyasu Sada
  • Patent number: 10050553
    Abstract: A rectifier circuit is described, which includes a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, an electronic circuit which includes at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor operated in the avalanche mode corresponding to the clamping voltage between the cathode terminal and the anode terminal of the rectifier circuit. In addition, a method is provided for operating a rectifier circuit which contains a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor being selected in accordance with the clamping voltage between the cathode terminal and the anode terminal, and the MOSFET transistor being operated in the avalanche mode.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 14, 2018
    Assignees: Robert Bosch GmbH, SEG Automotive Germany GmbH
    Inventors: Markus Baur, Alfred Goerlach
  • Patent number: 10014369
    Abstract: A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 3, 2018
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Sung-Nien Tang, Ho-Tai Chen, Hsiu-Wen Hsu
  • Patent number: 9997621
    Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 12, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Hitoshi Matsuura, Yuya Abiko
  • Patent number: 9997511
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 12, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9966406
    Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 9881927
    Abstract: CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Chia-Hong Jan, Walid M. Hafez, Joodong Park
  • Patent number: 9876106
    Abstract: A trench power transistor and a manufacturing method thereof are provided. The trench power transistor includes a substrate, an epitaxial layer, a trench gate structure, a body region, and a source region. The epitaxial layer disposed on the substrate has a trench formed therein. The trench gate structure disposed in the trench includes a bottom dielectric structure, a gate dielectric layer, and a gate. The bottom dielectric structure formed in a lower portion of the trench includes an insulating layer formed along a first inner wall of the lower portion of the trench defining a groove, and a non-conductive structure formed in the groove. The gate dielectric layer is formed along a second inner wall of an upper portion of the trench, and the gate is formed in the trench and connects the gate dielectric layer. The body region and the source region are formed in the epitaxial layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 23, 2018
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 9831231
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry L. Edwards, Akram A. Salman, Lili Yu
  • Patent number: 9812489
    Abstract: An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500° C. and 550° C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 7, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Daniel Tekleab