With Substrate And Lightly Doped Surface Layer Of Same Conductivity Type, Separated By Subsurface Heavily Doped Region Of Opposite Conductivity Type (e.g., "collector Diffused Isolation" Integrated Circuit) Patents (Class 257/549)
  • Patent number: 9478587
    Abstract: An array structure for light emitting diodes (LEDs) uses a patterned metal layer buried beneath LED chips to electrically interconnect non-adjacent chips in series, such that each chip in the LED array can be adjacently surrounded by LED chips of different colors. Thus, when the emission from the LED array is projected to a spot in the far field, its color uniformity over the spot is enhanced. Methods are also described for fabricating the multi-layer circuit board for such an array. Top and bottom patterned metal layers are formed, separated by a patterned insulating layer, so that electrical connections may be made between the metal layers. This provides “vias” between the metal layers for creating “cross-under” electrical connections under the second insulation layer, such that spatially-separated LED chips can be interconnected into strings, while maintaining electrical isolation between LED chips of different colors.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: October 25, 2016
    Assignee: DiCon Fiberoptics Inc.
    Inventors: Yao-Ren Liu, Ho-Shang Lee
  • Patent number: 9306034
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 5, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 9202940
    Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 1, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Yoshiyuki Nakaki, Yoshio Fujii, Hiroshi Watanabe, Shuhei Nakata, Kohei Ebihara, Akihiko Furukawa
  • Patent number: 9142687
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a first electrode, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, and a second electrode. The first electrode forms a Schottky junction with the first region. The second region is provided between the first region and the first electrode. The third region is provided between the first region and the first electrode and forms an ohmic junction with the first electrode. The fourth region is provided between the first region and the third region. The fourth region has a higher impurity concentration than the first region. The fifth region is provided between the third region and the first electrode. The fifth region has a higher impurity concentration than the third region. The second electrode is provided on opposite side of the first region from the first electrode.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichi Hori, Takao Noda, Kohei Morizuka, Ryoichi Ohara
  • Patent number: 8962406
    Abstract: An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8878310
    Abstract: An integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8455981
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: June 4, 2013
    Assignee: The Invention Science Fund I, LLC
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20120049274
    Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity, an epitaxial layer of a second conductivity on the substrate and a buried layer of the second conductivity interposed between the substrate and the epitaxial layer. A first trench structure extends through the epitaxial layer and the buried layer to the substrate and includes sidewall insulation and conductive material in electrical contact with the substrate at a bottom of the first trench structure. A second trench structure extends through the epitaxial layer to the buried layer and includes sidewall insulation and conductive material in electrical contact with the buried layer at a bottom of the second trench structure. A region of insulating material laterally extends from the conductive material of the first trench structure to the conductive material of the second trench structure and longitudinally extends to a substantial depth of the second trench structure.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Brahim Elattari, Franz Hirler
  • Patent number: 8106466
    Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.
    Type: Grant
    Filed: August 10, 2008
    Date of Patent: January 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Pin-Chien Chu
  • Patent number: 8106480
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: January 31, 2012
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 8084844
    Abstract: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takuji Tanaka
  • Patent number: 8068157
    Abstract: An image sensor includes a photoelectric converter, a source-follower transistor, and a selection transistor. The photoelectric converter generates electric charge in response to received light, and the electric charge varies a voltage of a detection node. The source-follower transistor is coupled between the detection node and an output node and has a first threshold voltage. The selection transistor is coupled between the source-follower transistor and a voltage node with a power supply voltage or a boosted voltage applied thereon, and has a second threshold voltage with a magnitude that is less than a magnitude of the first threshold voltage such that the source-follower transistor operates in saturation.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Il Jung, Min-Young Jung
  • Patent number: 8022496
    Abstract: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Alvin J. Joseph, Seong-dong Kim, Louis D. Lanzerotti, Xuefeng Liu, Robert M. Rassel
  • Patent number: 7994032
    Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: August 9, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yi Chiang, Chung Wang, Shou-Gwo Wuu, Dun-Nian Yaung
  • Patent number: 7898060
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 1, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 7791170
    Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: September 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yi Chiang, Chung Wang, Shou-Gwo Wuu, Dun-Nian Yaung
  • Patent number: 7776700
    Abstract: An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: August 17, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Veronique C. Macary, Jiang-Kai Zuo
  • Patent number: 7671384
    Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: March 2, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 7667288
    Abstract: Systems and methods for voltage distribution via epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises an epitaxial layer of a connectivity type disposed upon a wafer substrate of an opposite connectivity type.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 23, 2010
    Inventor: Robert P. Masleid
  • Patent number: 7622741
    Abstract: A semiconductor device of a double diffused MOS structure employing a silicon carbide semiconductor substrate. The semiconductor device comprises a silicon carbide semiconductor epitaxial layer provided on a surface of the silicon carbide semiconductor substrate and having a first conductivity which is the same conductivity as the silicon carbide semiconductor substrate, and an impurity region formed by doping a surface portion of the silicon carbide semiconductor epitaxial layer with an impurity of a second conductivity, the impurity region having a profile such that a near surface thereof has a relatively low second-conductivity impurity concentration and a deep portion thereof has a relatively high second-conductivity impurity concentration.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: November 24, 2009
    Assignee: Rohm Co., Ltd.
    Inventor: Mineo Miura
  • Patent number: 7560797
    Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: July 14, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Patent number: 7355259
    Abstract: Disclosed is a photodiode array which includes a plurality of p-i-n photodiodes arrayed on a semi-insulative semiconductor substrate, each photodiode including an n-type semiconductor layer grown on the substrate, an i-type semiconductor layer grown on the n-type semiconductor layer, a p-type semiconductor layer grown on the i-type semiconductor layer, an n-type electrode provided on the n-type semiconductor layer in a region exposed by partially removing the p-type semiconductor layer and the i-type semiconductor layer, and a p-type electrode provided on the p-type semiconductor layer. A trench is provided between the two adjacent photodiodes by partially removing the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer. Consequently, the size and pitch of the photodiodes can be decreased and crosstalk between the photodiodes can be reduced. Also disclosed is an optical receiver device including the photodiode array.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: April 8, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akira Yamaguchi, Yoshiki Kuhara
  • Patent number: 7202527
    Abstract: A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: April 10, 2007
    Assignee: Infineon Technologies AG
    Inventors: Kai Esmark, Harald Gossner, Gunther Mackh, Richard Owen, Franz Zängl
  • Patent number: 7026704
    Abstract: A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: April 11, 2006
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Ha Zoong Kim
  • Patent number: 7002222
    Abstract: An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: February 21, 2006
    Assignee: Infineon Technologies AG
    Inventor: Michael Bernhard Sommer
  • Patent number: 6953981
    Abstract: The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: October 11, 2005
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Ted Johansson, Arne Rydin, Christian Nyström
  • Patent number: 6897536
    Abstract: An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: May 24, 2005
    Assignee: Fujitsu Limited
    Inventors: Toshio Nomura, Teruo Suzuki
  • Patent number: 6867476
    Abstract: In a DMOS device, a drift region is located over a substrate and is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas are respectively located adjacent the source areas and in the body areas, and are heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: March 15, 2005
    Assignee: Samsung Electronics Co., LTD
    Inventor: Sun-Hak Lee
  • Patent number: 6847094
    Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: January 25, 2005
    Assignee: STMicroelectronics S.A.
    Inventor: Thierry Schwartzmann
  • Patent number: 6838745
    Abstract: An n-type well is formed in a p?-type semiconductor substrate and a p?-type epitaxial layer is formed on; the n-type well. An n?-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF operation. A p-type island is formed in the n?-type well at a position above the n-type well to form an island region for high withstand-voltage separation. Thus, the withstand voltage of the separated island is improved.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: January 4, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohide Terashima, Kazuhiro Shimizu
  • Patent number: 6835992
    Abstract: A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: December 28, 2004
    Assignee: Optical Communication Products, Inc.
    Inventors: Stanley E. Swirhun, Jeffrey W. Scott
  • Patent number: 6809790
    Abstract: A matrix substrate having, on a substrate, a plurality of electroconductive members to constitute pixel electrodes arrayed in a matrix pattern, and an electrically insulating member comprising a projecting region disposed between the electroconductive members to separate the pixel electrodes from each other, wherein a metal material having a higher melting point than that of the electroconductive members is placed at the base of the projecting region.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: October 26, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Yamagishi, Katsumi Kurematsu, Osamu Koyama, Toru Nakazawa
  • Patent number: 6784493
    Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
  • Patent number: 6710427
    Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, David D. Briggs, Dale Skelton
  • Patent number: 6707115
    Abstract: A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well implanted within a semiconductor substrate under the gate electrode; an n-well implanted in the p-well on the drain side; an n+ source region in the p-well outside of the n-well; an n+ drain region within the substrate inside the n-well; and lightly doped regions extending respectively from the source and drain regions toward the gate electrode.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 16, 2004
    Assignee: AirIP Corporation
    Inventor: Dominik J. Schmidt
  • Patent number: 6664608
    Abstract: A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 16, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: James B. Burr
  • Patent number: 6664607
    Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p-type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: December 16, 2003
    Assignee: NEC Corporation
    Inventor: Tomonobu Yoshitake
  • Publication number: 20030227070
    Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 11, 2003
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, David D. Briggs, Dale Skelton
  • Patent number: 6653708
    Abstract: A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at −V (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: November 25, 2003
    Assignee: Intersil Americas Inc.
    Inventor: Brent R. Doyle
  • Patent number: 6636402
    Abstract: A high voltage protection circuit (20) in a non-volatile memory includes a first transistor (22) and a second transistor (24) each formed in their own separate wells. A high voltage supply (Vhv) is provided at the drain of the second transistor (24). The source (40) of second transistor (24) is connected to the drain of first transistor (22) and to well (32), and the gate of the second transistor (24) is connected to Vdd, the main power supply to the chip. By forming the transistors in their own separate wells with the source of the second transistor (24) connected to its own well, breakdown of the circuit is governed by the sum of BVdss of the first transistor (22) and a gate induced breakdown (BVind) of the second transistor (24). With this circuit use of even a low Vdd (e.g. <3V) on the gate of the second transistor (24) is sufficient to protect against unwanted exposure to Vhs or to prevent leakage so that a higher stand-off voltage need not be generated and routed to the circuit.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: October 21, 2003
    Assignee: Motorola, Inc.
    Inventors: Alexis Marquot, Philippe Bauser
  • Patent number: 6627928
    Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: September 30, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniela Peschiaroli, Alfonso Maurelli, Elisabetta Palumbo, Fausto Piazza
  • Patent number: 6614067
    Abstract: A process for fabricating a polysilicon dual gate structure, featuring the use of a tungsten plug structure, used to alleviate the diode effect, present at the dopant interface in the polysilicon dual gate structure, has been developed. A first iteration of this invention places the tungsten plug, on a portion of a metal silicide layer, in a region directly overlying the dopant interface, (N type-P type regions), in the polysilicon dual gate structure. A second iteration of this invention places the tungsten plug directly on the dopant interface of the polysilicon dual gate structure, with the tungsten plug structure formed in a borderless opening, in an insulator layer. The use of the tungsten plug allows a less resistive current path through the polysilicon dual gate structure, when compared to counterparts fabricated without the tungsten plug structure, in which a more resistive current path, through a diode present at dopant interface, exists.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 2, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jhon-Jhy Liaw
  • Patent number: 6614087
    Abstract: An object is to provide a semiconductor device which is free from such voltage oscillation as may cause malfunction of peripheral equipment. In a semiconductor device having a pin structure, the impurity concentration gradient in an n+ layer (103) serving as a buffer layer is set equal to or less than 2×1018cm−4. Then, when a reverse bias voltage is applied and a depletion layer reaches the n+ layer (103), the expansion of the depletion layer is prevented from rapidly stopping and the voltage oscillation can be suppressed.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: September 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Morishita, Katsumi Satoh, Noritoshi Hirano
  • Patent number: 6600188
    Abstract: An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located at the polysilicon edges of the tunnel window. During the programming operation, the P-type lightly-doped drain regions are in contacting with the polysilicon edges. As a result, there is reduced or suppressed the tunneling current to the program junction region so as to improve the efficiency of programming.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: July 29, 2003
    Assignee: Lattice Semiconductor Corporation
    Inventors: Chun Jiang, Sunil D. Mehta
  • Patent number: 6580149
    Abstract: An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: June 17, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Mark McQueen, Robert Kerr
  • Publication number: 20030102524
    Abstract: A low noise microwave MOSFET fabricated with source-side halo implantation. The dopant concentration has an asymmetrical horizontal profile along the channel from the source to the drain.
    Type: Application
    Filed: January 14, 2003
    Publication date: June 5, 2003
    Inventor: Luiz M. Franca-Neto
  • Patent number: 6573582
    Abstract: A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: June 3, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasunori Yamashita, Fumitoshi Yamamoto, Tomohide Terashima
  • Patent number: 6563181
    Abstract: A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: May 13, 2003
    Assignee: Motorola, Inc.
    Inventors: Yang Du, Suman Kumar Banerjee, Rainer Thoma, Alain Duvallet
  • Patent number: 6504230
    Abstract: A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: January 7, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Hans-Joachim Schulze, Anton Mauder, Helmut Strack
  • Patent number: 6469365
    Abstract: A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more highly doped edge layer of the second conductivity type are disposed at the surface of the substrate and are isolated from one another by pn junctions. At least one of the wells is completely surrounded by an insulating well of the first conductivity type. The doping of the insulating well is higher than that of the substrate. A method for fabricating a semiconductor component is also provided.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: October 22, 2002
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Werner