Abstract: First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in concentration than that of the first conductivity type impurities are injected into a predetermined region in the first conductivity type region to selectively form a second conductivity type region. Then, first conductivity type impurities are selectively injected into the second conductivity type region to selectively form a lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.

Abstract: A low junction capacitance semiconductor structure and an I/O buffer are disclosed. The semiconductor structure includes a MOS transistor and a lightly doped region. The MOS transistor is formed in a semiconductor substrate and has a gate and source and drain region formed aside the gate. The lightly doped region has a conductivity the same as the source and drain regions, and is formed in the drain region and has a depth larger than the source and drain regions. Further, the lightly doped region can be achieved by CMOS-compatible processes, and the formed devices in the well can be isolated from the semiconductor substrate using deeply doped regions which are usually adopted in advanced technologies.

Abstract: A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The drain impurity distribution is substantially contained within a detached drain region of the semiconductor substrate. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between the source region of the semiconductor substrate and the detached drain region. The channel boundary of the detached drain region is laterally displaced from a first sidewall of the conductive gate by a detached displacement. Preferably, the gate dielectric is a thermal oxide having a thickness of approximately 20 to 200 angstroms.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions.

Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions.

Abstract: A current source formed in a p-type substrate is disclose. First, a deep n-well is formed within the p-type substrate and a buried n+ layer is formed within the deep n-well. Next, a p-well is formed within the deep n-well and atop the buried n+ layer. The p-well and deep n-well are then surrounded by an isolation structure that extends from the surface of the substrate to below the level of the p-well. A n+ reference structure is formed within the p-well and a gate is formed above the p-well, the gate separated from the substrate by a thin oxide layer, the gate extending over at least a portion of the n+ reference structure. Finally, a n+ output structure is formed within the p-well. An input reference current is provided to the n+ reference structure and an output current is provided by the n+ output structure.

Abstract: An inductive component includes a substrate on the surface of which is a lower insulation layer having a shallow concavity or trench, a first plurality of conductive elements formed in the trench, a magnetic core formed over the first plurality of conductive elements, and a second plurality of conductive elements formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques. A first array of conductors is patterned over the lower insulation layer, and a first core insulation layer is applied over the first conductor array. A magnetic core is formed on top of the first core insulation layer, and a second core insulation layer is applied over the core.

Abstract: The invention relates to a half-bridge circuit comprising two series-connected n-channel DMOS transistors, in which the source of the one transistor, the low-side transistor T.sub.1, is connected to a low-voltage terminal V.sub.ss, and the drain of the other transistor, the high-side transistor T.sub.2, is connected to a high-voltage terminal V.sub.dd. The drain of the low-side transistor and the source of the high-side transistor are connected to the output terminal (4). The circuit is arranged in a semiconductor body having an n-type or p-type epitaxial layer (11) which is applied to a p-type substrate (10). In the epitaxial layer, two n-type regions are defined for the transistors, each of said regions forming a drift region of one of the transistors and being surrounded by a cup-shaped n-type zone in the semiconductor body. Within the n-type cup-shaped zone (12) of the low-side transistor T.sub.1, there is provided a p-type cup-shaped zone which isolates the drift region (15) of T.sub.

Abstract: A Bi-CMOS semiconductor device having a CMOS device region and a bipolar transistor region is provided wherein the bipolar transistor has a collector region of a first conductivity type and the CMOS region has at least one element region of a second conductivity type which is positioned adjacent to the collector region as well as wherein a single buried layer of the first conductivity type is provided which extends under the element region of the CMOS region and the collector region.

Abstract: The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by diffusion from the top side (14) of the substrate (12). Further, the transistor comprises a second region (18) arranged within the n-conducting region (16), which is n-doped and introduced into the substrate from the top side (14) of the substrate (12), and a field oxide layer (20) which is arranged on the top side (14) of the substrate (12) and limits the p-conducting region (16) on all sides. The top side comprises a source region (22) and a drain region (24) which are n-doped and arranged within the p-conducting region (18) at a distance to each other. A gate oxide layer (26) is arranged on the top side (14) of the substrate (12) between the source and the drain regions (22, 24).

Abstract: An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog devices are formed over the rest of the substrate and operate between plus and minus 5 volts. The moat 9505 isolates the digital CMOS devices from the analog devices.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).

Abstract: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate.

Abstract: In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Abstract: In a nonvolatile memory device and manufacturing method, the device includes cell transistors having sources and drains shared by cell transistors adjacent in a first direction, a floating gate confined to the respective cell transistors, and a control gate shared by cell transistors adjacent in a second direction, first plugged conductive layers formed in a long rod shape in the second direction so that sources of cell transistors adjacent in the second direction are connected with one another, second plugged conductive layers each connected with drains of the respective cell transistors, a common source line formed in a long rod shape in the second direction so as to be connected with the first plugged conductive layers thereon, a pad layer formed so as to be confined to the respective cell transistors on the second plugged conductive layers, and a bit line connected with the pad layer through a contact hole. Therefore, the improvement of integration of a memory device can be easily attained.

Abstract: A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.

Abstract: A composite semiconductor device comprised of a power MOS FET and a low level signal element. The MOS FET includes an n type buried layer embedded between p type substrate and n type epitaxial layer. As conventionally formed due to the pn junctions between the p substrate and the n epitaxial layer, and between the p substrate and the n buried layer, the depletion layers had abrupt transitions therebetween, inviting field concentrations and consequent voltage drops. In order to mitigate the abrupt transitions, one or more n type additional buried regions are provided in and between the substrate and the epitaxial layer and in the adjacency of the buried layer. The additional buried regions are higher in impurity concentration than the epitaxial layer.

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: A silicon starting material for fabricating integrated circuits is desrcibed that comprises a silicon wafer substrate material and a first epitaxial layer grown on the wafer substrate material which eliminates stacking faults in the subsequent fabrication of a semiconductor device.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: In an integrated circuit, a wraparound isolation region capable of sustaining a high blocking voltage to a substrate encloses a variety of high voltage or low voltage device.

Abstract: A Flash EEPROM memory array includes a plurality of transistor memory cells (24) arranged in rows and columns. The sources of the transistors (24) are connected to Virtual Ground Lines (29) and the drains thereof are connected to Column Lines (28). The memory cells (24) are programmable by Fowler-Nordheim tunneling. Each cell also includes an isolation structure having a first isolation tank of the first conductivity type material for surrounding each of the floating gate transistor memory devices and a second isolation tank of a second conductivity type material opposite to the first conductivity type surrounding the first isolation tank, allowing application of a negative voltage to the source or drain of the cell. Initially, all of the transistors are erased in the FLASH ERASE operation by disposing the Word Lines at a negative medium voltage and the Bit Lines at a positive medium voltage. Thereafter, selected transistors can be written to by selectively charging the floating gates in the transistors.

Abstract: A lateral static induction transistor suited for use as a picture element of a solid state imaging device. The lateral static induction transistor includes a semiconductor substrate of a first conduction type of P type or N type, a first epitaxial layer of the same conduction type as the first conduction type which is formed on the semiconductor substrate, a second epitaxial layer of a second conduction type opposite to the first conduction type which is formed on the first epitaxial layer, a source zone and a plurality of drain zones which are formed in the second epitaxial layer near the surface thereof, and a plurality of gates each thereof being formed so as to partially lie over the source zone and one of the drain zones on the second epitaxial layer through an insulating layer.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: A high density substrate plate trench DRAM cell memory device and process are described in which a buried region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is contacted along its perimeter by a reach through region to complete the isolation. The combined regions reduce charge loss due to better control of device parasitics.

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.

Abstract: An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.

Abstract: A power transistor having an epitaxial layer within an isolation region is formed in a semiconductor substrate. A buried diffusion within the substrate with vertical diffusions contacting it form the isolation region. A drain, source, gate, and drift region are formed within the epitaxial layer such that a RESURF LDMOS transistor is formed having its source isolated from the substrate. Multiple power transistors may share the buried isolation region. A P type semiconductor substrate allows the power transistor and high performance CMOS circuitry to be formed on the same semiconductor die.

Abstract: A semiconductor structure (30) is provided for electrostatic discharge protection. A first bipolar transistor (Q1) has a collector electrically coupled to a first node (12), a base electrically coupled to a second node, and an emitter electrically coupled to a third node (14). A second bipolar transistor (Q2) has a collector, a base electrically coupled to the second node, and an emitter electrically coupled to the first node (14). The second bipolar transistor (Q2) supplies a base current to the base of the first bipolar transistor (Q1) in response to the first node (12) reaching a threshold voltage relative to the third node (14), so that the first bipolar transistor (Q1) conducts current between the first (12) and third (14) nodes in response to the base current.

Abstract: A semiconductor device wherein a bipolar transistor and a junction type field effect transistor which has a high voltage resisting property and a high mutual conductance are formed into a single chip to reduce the cost. A bipolar transistor formation region is separated from a junction type field effect transistor formation region by a transistor separating region. In the former region, a collector diffused layer is formed on the semiconductor substrate on which an epitaxial layer is formed, and a base diffused layer and a collector lead diffused layer are formed in the epitaxial layer with an element separating region interposed therebetween and connect to the collector diffused layer. Further, an emitter diffused layer is formed on the base diffused layer. In the latter region, a bottom gate diffused layer is formed on the semiconductor substrate, and a channel formation region is formed in the epitaxial layer and connects to the bottom gate diffused layer.

Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches.

Abstract: A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.