With Lightly Doped Surface Layer Of One Conductivity Type On Substrate Of Opposite Conductivity Type, Having Plural Heavily Doped Portions Of The One Conductivity Type Between The Layer And Substrate, Different Ones Of The Heavily Doped Portions Having Differing Depths Or Physical Extent Patents (Class 257/550)
  • Patent number: 8921978
    Abstract: An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 ?m and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Hsiao-Chun Lee
  • Patent number: 8901713
    Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8878310
    Abstract: An integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8796818
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 8779527
    Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas Merelle, Gerben Doornbos, Robert James Pascoe Lander
  • Patent number: 8723291
    Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Yonezu, Takeshi Iwamoto, Shigeki Obayashi, Masashi Arakawa, Kazushi Kono
  • Patent number: 8587027
    Abstract: A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers 3 and 7, undoped AlGaAs spacer layers 4 and 6, and an undoped InGaAs channel layer 5) formed above a semi-insulating GaAs substrate, an upper semiconductor layer made up of at least one semiconductor layer and formed above the channel layer of the first conductivity type, a semiconductor layer of a second conductivity type (C-doped p+-GaAs layer 18) formed in a recess made in the upper semiconductor layer or formed above the upper semiconductor layer, a gate electrode placed above and in contact with the semiconductor layer of the second conductivity type, and a gate insulating film including a nitride film formed above and in contact with the upper semiconductor layer and an oxide film formed above the nitride film and having a larger thickness than the nitride film.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yasunori Bito
  • Patent number: 8304827
    Abstract: A semiconductor device includes a diode formed by making use of a DMOS transistor structure. In addition to such a DMOS transistor structure, the semiconductor device includes a second buried layer of the first conductivity type being provided on a first buried layer of a second conductivity type that is in a floating state. Moreover, the second buried layer of the first conductivity type and a second diffusion region of the first conductive type are connected by a first diffusion region of the first conductivity type. A first electrode is set as anode, and a second electrode and a third electrode are short-circuited and set as cathode.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: November 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Nakamura, Koji Shirai, Hirofumi Nagano, Jun Morioka, Tsubasa Yamada, Kazuaki Yamaura, Yasunori Iwatsu
  • Patent number: 8283231
    Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: October 9, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas Merelle, Gerben Doornbos, Robert James Pascoe Lander
  • Patent number: 8106466
    Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.
    Type: Grant
    Filed: August 10, 2008
    Date of Patent: January 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Pin-Chien Chu
  • Patent number: 8084844
    Abstract: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takuji Tanaka
  • Patent number: 8084791
    Abstract: In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 27, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Yen-Hao Shih
  • Patent number: 8072043
    Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 6, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Peter Flohrs, Alfred Goerlach, Peter Urbach, Wolfgang Feiler, Ning Qu, Klaus Heyers
  • Patent number: 7939897
    Abstract: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Prasad Venkatraman
  • Patent number: 7923756
    Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.
    Type: Grant
    Filed: May 31, 2008
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hironobu Fukui
  • Patent number: 7763956
    Abstract: A semiconductor device and a method of fabricating same are provided. According to an embodiment, a gate insulating layer and a gate are sequentially formed on a substrate, and a pocket ion implant region is formed at sides and below a portion of the gate at a predetermined depth in the substrate. An LDD ion implant region can be formed between the pocket ion implant region and the surface of the substrate. A spacer is formed on sides of the gate, and a deep source/drain region is formed by ion-implanting BF2 within the substrate at sides of the spacer.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 27, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Haeng Leem Jeon
  • Patent number: 7741699
    Abstract: A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: June 22, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keh-Chiang Ku, Chun-Feng Nieh, Li-Ping Huang, Chih-Chiang Wang, Chien-Hao Chen, Hsun Chang, Li-Ting Wang, Tze-Liang Lee, Shih-Chang Chen
  • Patent number: 7560797
    Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: July 14, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Patent number: 7449744
    Abstract: A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: November 11, 2008
    Assignee: Nanostar Corporation
    Inventors: Andy Yu, Ying W. Go
  • Patent number: 7432581
    Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: October 7, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiki Kanamoto, Masumi Yoshida, Tetsuya Watanabe, Takashi Ippoushi
  • Patent number: 7202527
    Abstract: A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: April 10, 2007
    Assignee: Infineon Technologies AG
    Inventors: Kai Esmark, Harald Gossner, Gunther Mackh, Richard Owen, Franz Zängl
  • Patent number: 7064413
    Abstract: A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substrate; implanting dopant ions into the exposed vertical surfaces of the at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into the exposed vertical surfaces of the at least one semiconductor body without saturation; and forming contacts to the at least one semiconductor body. The present invention is directed to a Fin structure which includes a resistor present within the thin vertically oriented semiconductor body.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: June 20, 2006
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Edward J. Nowak
  • Patent number: 7002222
    Abstract: An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: February 21, 2006
    Assignee: Infineon Technologies AG
    Inventor: Michael Bernhard Sommer
  • Patent number: 7002218
    Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N? well is located substantially under the N+ and P+ diffusions.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: February 21, 2006
    Assignee: Microchip Technology Incorporated
    Inventor: Randy L. Yach
  • Patent number: 6940110
    Abstract: A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate insulation film, a gate electrode and the like. In the storage-type SiC-MISFET, a partially heavily doped layer is formed by partially implanting ions of a p-type impurity into an upper surface portion of the n-type drift layer and containing an impurity of the same conductive type as that of the impurity implanted into the well region at a higher concentration than that in the well region.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: September 6, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kunimasa Takahashi, Osamu Kusumoto, Makoto Kitabatake, Masao Uchida, Kenya Yamashita
  • Patent number: 6864559
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6770950
    Abstract: A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 3, 2004
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Song Yang, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 6762461
    Abstract: A protective circuit for protecting an IGBT from a stress due to application of an overvoltage which is induced by a surge such as static electricity is provided. The protective circuit allows for improvement in a voltage tolerance to a stress due to application of an overvoltage induced by a surge while ensuring a current tolerance to flow of a direct current from an external power supply when the external power supply is improperly connected in a direction contrary to a normal direction. The protective circuit includes a resistor having one end connected to a terminal for connecting to the external power supply and the other end connected to a semiconductor element, and a first zener diode including a cathode connected to the other end of the resistor. The protective circuit further includes a plurality of second zener diodes connected in series between the one end of the resistor and a generator of a constant potential such as a ground.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: July 13, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsunobu Kawamoto
  • Patent number: 6740958
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: May 25, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6730959
    Abstract: A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 4, 2004
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Chih-Wei Hung, Da Sung, Chih-Ming Chen
  • Patent number: 6707115
    Abstract: A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well implanted within a semiconductor substrate under the gate electrode; an n-well implanted in the p-well on the drain side; an n+ source region in the p-well outside of the n-well; an n+ drain region within the substrate inside the n-well; and lightly doped regions extending respectively from the source and drain regions toward the gate electrode.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 16, 2004
    Assignee: AirIP Corporation
    Inventor: Dominik J. Schmidt
  • Publication number: 20030173646
    Abstract: A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 18, 2003
    Inventors: Ching-Song Yang, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 6614067
    Abstract: A process for fabricating a polysilicon dual gate structure, featuring the use of a tungsten plug structure, used to alleviate the diode effect, present at the dopant interface in the polysilicon dual gate structure, has been developed. A first iteration of this invention places the tungsten plug, on a portion of a metal silicide layer, in a region directly overlying the dopant interface, (N type-P type regions), in the polysilicon dual gate structure. A second iteration of this invention places the tungsten plug directly on the dopant interface of the polysilicon dual gate structure, with the tungsten plug structure formed in a borderless opening, in an insulator layer. The use of the tungsten plug allows a less resistive current path through the polysilicon dual gate structure, when compared to counterparts fabricated without the tungsten plug structure, in which a more resistive current path, through a diode present at dopant interface, exists.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 2, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jhon-Jhy Liaw
  • Patent number: 6563181
    Abstract: A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: May 13, 2003
    Assignee: Motorola, Inc.
    Inventors: Yang Du, Suman Kumar Banerjee, Rainer Thoma, Alain Duvallet
  • Patent number: 6504230
    Abstract: A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: January 7, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Hans-Joachim Schulze, Anton Mauder, Helmut Strack
  • Publication number: 20030001233
    Abstract: A semiconductor memory device of the present invention includes: a substrate; a plurality of memory cells arranged in a matrix pattern on a primary surface of the substrate; a sense amplifier provided in each column for detecting data of the memory cells that are arranged along the column; a plurality of wiring layers formed on the substrate; and a plurality of data lines provided in each column and connected to the memory cells that are arranged in the column, wherein the data lines are connected commonly to the sense amplifier but via different paths, and a data line having a longer path length is provided by using a wiring layer that is on a higher level.
    Type: Application
    Filed: June 17, 2002
    Publication date: January 2, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Yamauchi
  • Patent number: 6501147
    Abstract: A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: December 31, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Bruno Vajana, Matteo Patelmo
  • Patent number: 6492679
    Abstract: A high voltage MOSFET device (100) has a well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate region (105). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the “on” state. The MOSFET device further has a p-top layer (108) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: December 10, 2002
    Assignee: Semiconductor Components Industries LLC
    Inventors: Mohamed Imam, Joe Fulton, Zia Hossain, Masami Tanaka, Taku Yamamoto, Yoshio Enosawa, Katsuya Yamazaki, Evgueniy N. Stefanov
  • Patent number: 6480639
    Abstract: In an optical module having a silicon substrate, a plurality of optical semiconductor devices and optical waveguides for performing transmission of optical signals by the semiconductor devices integrated on the silicon substrate, the silicon substrate is doped with an impurity to increase the number of carriers in the silicon substrate for suppressing optical crosstalk between the plurality of optical semiconductor devices, the optical waveguide is composed of a core part and a peripheral cladding layer of the core part, or optical fibers each coupled with each of the semiconductor devices, and an electrical resistivity of part or all of the silicon substrate is 0.
    Type: Grant
    Filed: September 22, 1998
    Date of Patent: November 12, 2002
    Assignee: Nippon Telegraph and Telephone Corp.
    Inventors: Toshikazu Hashimoto, Yasufumi Yamada, Masahiro Yanagisawa, Kuniharu Kato, Yasuyuki Inoue
  • Patent number: 6426535
    Abstract: First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in concentration than that of the first conductivity type impurities are injected into a predetermined region in the first conductivity type region to selectively form a second conductivity type region. Then, first conductivity type impurities are selectively injected into the second conductivity type region to selectively form a lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventors: Kiyoshi Takeuchi, Shigetaka Kumashiro
  • Publication number: 20020089030
    Abstract: In a semiconductor substrate, functional circuit structures and dummy structures are bounded by an insulation well that includes a buried diffusion region and a peripherally encompassing depth diffusion. A peripheral contact diffusion is additionally provided within a surface region defined by the depth diffusion.
    Type: Application
    Filed: November 2, 2001
    Publication date: July 11, 2002
    Inventor: Sabine Kling
  • Publication number: 20020070413
    Abstract: First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in concentration than that of the first conductivity type impurities are injected into a predetermined region in the first conductivity type region to selectively form a second conductivity type region. Then, first conductivity type impurities are selectively injected into the second conductivity type region to selectively form a lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.
    Type: Application
    Filed: October 4, 1999
    Publication date: June 13, 2002
    Inventors: KIYOSHI TAKEUCHI, SHIGETAKA KUMASHIRO
  • Patent number: 6388298
    Abstract: A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The drain impurity distribution is substantially contained within a detached drain region of the semiconductor substrate. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between the source region of the semiconductor substrate and the detached drain region. The channel boundary of the detached drain region is laterally displaced from a first sidewall of the conductive gate by a detached displacement. Preferably, the gate dielectric is a thermal oxide having a thickness of approximately 20 to 200 angstroms.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 14, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr.
  • Patent number: 6376870
    Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: April 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: John H. Carpenter, Jr., Joseph A. Devore, Toru Tanaka, Ross E. Teggatz
  • Patent number: 6281521
    Abstract: Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a “pinched off” gate region when no bias is applied to the gate. In particular embodiments of the present invention, the semiconductor devices include a silicon carbide drift layer of a first conductivity type, the silicon carbide drift layer having a first face and having a channel region therein. A buried base region of a second conductivity type semiconductor material is provided in the silicon carbide drift layer so as to define the channel region. A gate layer of a second conductivity type semiconductor material is formed on the first face of the silicon carbide drift layer adjacent the channel region of the silicon carbide drift layer. A gate contact may also be formed on the gate layer. Both transistors and thyristors may be provided.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: August 28, 2001
    Assignee: Cree Research Inc.
    Inventor: Ranbir Singh
  • Patent number: 6274909
    Abstract: In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 14, 2001
    Assignee: Etron Technology, Inc.
    Inventors: Kun-Zen Chang, Deng-Shun Chang, Rong-Tai Kao
  • Patent number: 6194776
    Abstract: A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: February 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Teruhiko Amano, Masaki Tsukude
  • Patent number: 6168983
    Abstract: A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: January 2, 2001
    Assignee: Power Integrations, Inc.
    Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
  • Patent number: 6064077
    Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: May 16, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Ravishankar Sandaresan
  • Patent number: 6028342
    Abstract: A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon nitride layer is over the N well. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The N well is doped using first P-type ions to form a plurality of essentially parallel P-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the P-pole regions. The N well is doped and annealed, to form a plurality of P-type diffusion regions under the exposed portions of the P-pole regions. The P-pole regions are doped and annealed, to form a plurality of N-type diffusion regions in the exposed portions of the P-pole regions. A metal layer is formed which fills the contact windows.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: February 22, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Kuang-Yeh Chang