Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract: A semiconductor device includes a power transistor group and a signal circuit on the same substrate. The substrate is grounded at an isolation region at an end of the substrate adjacent to the power transistor group so that the grounded portion of the substrate is distant from the signal circuit.

Abstract: In a nonvolatile memory device and manufacturing method, the device includes cell transistors having sources and drains shared by cell transistors adjacent in a first direction, a floating gate confined to the respective cell transistors, and a control gate shared by cell transistors adjacent in a second direction, first plugged conductive layers formed in a long rod shape in the second direction so that sources of cell transistors adjacent in the second direction are connected with one another, second plugged conductive layers each connected with drains of the respective cell transistors, a common source line formed in a long rod shape in the second direction so as to be connected with the first plugged conductive layers thereon, a pad layer formed so as to be confined to the respective cell transistors on the second plugged conductive layers, and a bit line connected with the pad layer through a contact hole. Therefore, the improvement of integration of a memory device can be easily attained.

Abstract: A semiconductor device relating to an improvement in an L-PNP transistor in particular is such that, on a semiconductor substrate of a first conductivity type, a base region is formed which has a second conductivity type opposite in conductivity to the first conductivity type. A first conductivity type impurity ion is implanted into the base region to provide at least two first diffusion layers there. The first diffusion layers have a first impurity concentration level and are formed as collector and emitter regions. A polysilicon layer is formed on the first diffusion layer in base region in an overhanging relation to the first diffusion layer and contains the first conductivity type impurity. A second diffusion layer is formed around the collector region and around the emitter region by diffusing an impurity from the polysilicon layer. The collector and emitter regions each are formed as a two-layered structure with their first and second diffusion layers.

Abstract: A surface voltage sustaining structure around an n.sup.+ (or p.sup.+)-type region on a p.sup.- (or n.sup.-)-type substrate for high-voltage devices is made by a combination of n-type regions and/or p-type regions and produces an effective surface density of donor (or acceptor) decreasing with the distance to the n.sup.+ (or p.sup.+)-type region on the surface, when all of the regions are depleted under reverse breakdown voltage. The surface voltage sustaining structure can make the breakdown voltage of the n.sup.+ -p.sup.- (or p.sup.+ -n.sup.-)-junction reach more than 90% of that one-sided parallel plane junction with the same substrate doping concentration. High-voltage vertical devices as well as high-voltage lateral devices with fast response, low on-voltage and high current density can be made by using this invention.

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit.The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

Abstract: A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: A large sense voltage is produced by the semiconductor device of the present invention. The semiconductor device, utilizing current mirror techniques, is comprised of a power MOSFET having a plurality of power cells and a plurality of sense cells formed in a semiconductor epitaxial layer. The large sense voltage is provided by isolating and separating the plurality of power cells from the plurality of sense cells by at least the thickness of the semiconductor epitaxial layer. Isolation can be provided by forming a plurality of inactive cells or an elongated cell between the plurality of power cells and the plurality of sense cells. In addition, high voltage capabilities can be maintained by including a partially active region adjacent the power cells to provide for good termination.

Abstract: A silicon starting material for fabricating integrated circuits is desrcibed that comprises a silicon wafer substrate material and a first epitaxial layer grown on the wafer substrate material which eliminates stacking faults in the subsequent fabrication of a semiconductor device.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.

Abstract: An isolation structure is provided to give improved protection from below ground current injection. A first epitaxial region is provided between a power field effect device and nearby control circuitry. The first epitaxial region is tied to the substrate, and the ties are located between the first epitaxial region and the power field effect device. On the opposite side of the power device, preferably adjacent an edge of the integrated circuit chip, a second epitaxial region is formed. This epitaxial region is connected to the first epitaxial region, preferably by a metal interconnect line. A second set of substrate contacts is located between the power device and the second epitaxial region, and is tied to ground. The second epitaxial region encourages injection of current at a location spaced away from the control circuitry.

Abstract: An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.

Abstract: A semiconductor integrated circuit device is fabricated from a complementary inverter circuit and an emitter coupled logic circuit, and an n-type well assigned to a p-channel type transistor extends beneath a p-type well assigned to an n-channel type transistor for partially overlapping therewith, thereby increasing capacitance across the p-n junction for eliminating noises from power voltages.

Abstract: A semiconductor device composed of a substrate provided with a groove filled with insulating material to define an element isolating region. The groove corners are rounded and the substrate contains impurity material below the groove and in a region adjacent the groove. The impurity material is introduced to have essentially the same impurity density profile below the bottom of the groove and below the substrate surface in the region adjacent the groove.The device may additionally be provided, if the region below and adjacent the groove is of P-type conductivity, with a buried P-type layer which opposes penetration of .alpha. particle radiation into the substrate.

Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tub, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.