Complementary Bipolar Transistor Structures (e.g., Integrated Injection Logic, I 2 L) Patents (Class 257/555)
  • Patent number: 9537438
    Abstract: A genset includes a generator configured to generate a power signal having a first voltage. A controller is configured to monitor and control at least one operational parameter of the generator. A buss potential isolation module is configured to receive the power signal having the first voltage from the generator, reduce the first voltage to output a second voltage, and communicate the power signal having the second voltage to the controller. The second voltage is suitable for communicating to the controller which can include electronic circuitry configured to meet an NEC Class 2 circuit requirement. The first voltage can be at least 120 volts, and the second voltage can be less than 24 volts.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 3, 2017
    Assignee: Cummins Power Generation, IP, Inc.
    Inventor: Brian B. Brady
  • Patent number: 8330223
    Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Klaus Schimpf, Manfred Schiekofer, Carl David Willis, Michael Waitschull, Wolfgang Ploss
  • Patent number: 8115256
    Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: February 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Haruki Yoneda, Hideaki Fujiwara
  • Patent number: 8030731
    Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: October 4, 2011
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 8026569
    Abstract: In one embodiment of the present invention, a semiconductor device has a photodiode over a P-type substrate, an NPN transistor formed over the P-type substrate, an N+-type buried region provided right under the NPN transistor as being buried in the P-type substrate, and a P+-type buried region formed in the N+-type buried region.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: September 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Miura
  • Patent number: 7732800
    Abstract: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 8, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh Kun Lai, Chia Hua Ho, Kuang Yeu Hsieh
  • Patent number: 7675140
    Abstract: An N-type diffusion layer fixed at a potential equal to or above 0V is provided in a segregating region between terminals, and a P-type diffusion layer having a potential equal to that of the N-type diffusion layer on an N-type well constitute a drain of a transistor.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: March 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Shuichiro Kojima, Mamoru Seike, Takashi Ichihara
  • Patent number: 7619299
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. In the substrate and the epitaxial layer, an N type buried diffusion layer is formed on a P type buried diffusion layer. With this structure, an upward expansion of the P type buried diffusion layer is checked and a thickness of the epitaxial layer can be made small while maintaining the breakdown voltage characteristics of a power semiconductor element. Accordingly, a device size of a control semiconductor element can be reduced.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: November 17, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Keiji Mita, Kentaro Ooka
  • Patent number: 7518194
    Abstract: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.
    Type: Grant
    Filed: May 20, 2006
    Date of Patent: April 14, 2009
    Inventors: Sergey Antonov, Alexei I Antonov
  • Patent number: 7345347
    Abstract: At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well located closer to the bottom side of the p-type Si substrate than the p-type well, so as to isolate the p-type well from a bottom-side region of the p-type Si substrate. The deep n-type well includes a first deep n-type well. The deep n-type well includes a second deep n-type well located closer to the bottom side of the p-type Si substrate than the first deep n-type well, and having an n-type impurity concentration, which is different from the first deep n-type well.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 18, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Patent number: 7342293
    Abstract: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 11, 2008
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Wallner, Thomas N. Adam, Stephen W. Bedell, Joel P. De Souza
  • Patent number: 7265434
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: September 4, 2007
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Patent number: 7129562
    Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: October 31, 2006
    Assignee: Virage Logic Corporation
    Inventors: Tushar R. Gheewala, Michael J. Colwell, Henry H. Yang, Duane G. Breid
  • Patent number: 7026690
    Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 6992338
    Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: January 31, 2006
    Assignee: Newport Fab, LLC
    Inventors: Kevin Q. Yin, Amol Kalburge, Klaus F. Schuegraf
  • Patent number: 6809396
    Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: October 26, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peter J. Zdebel, Misbahul Azam, Gary H. Loechelt, James R. Morgan, Julio C. Costa
  • Patent number: 6717235
    Abstract: The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive SFFs are connected, respectively, to the input pads and the output pads directly or via the combination circuit. In this configuration, the output pads and the input pads are connected to each other inside the chip to thereby form a test path.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: April 6, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tatsunori Komoike
  • Patent number: 6569730
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: May 27, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
  • Publication number: 20030080394
    Abstract: An integrated circuit and a method of fabricating the same are disclosed. Complementary bipolar transistors (20p, 20n) are fabricated as vertical bipolar transistors. The emitter polysilicon (35), which is in contact with the underlying single-crystal base material, is doped with a dopant for the appropriate device conductivity type, and also with a diffusion retardant, such as elemental carbon, SiGeC, nitrogen, and the like. The diffusion retardant prevents the dopant from diffusing too fast from the emitter polysilicon (35). Device matching and balance is facilitated, especially for complementary technologies.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 1, 2003
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Leland Swanson, Scott G. Balster, Gregory E. Howard, Alfred Hausler
  • Publication number: 20030057521
    Abstract: A semiconductor structure used for fabricating bipolar transistors. A semiconductor structure is composed of a substrate, and a layered semiconductor structure. The layered semiconductor structure consists of a first layer covering the substrate, a second layer covering the first layer, and a third layer covering the second layer. The first layer includes a first semiconductor layer of a first conductivity type. The second layer includes a second semiconductor layer of a second conductivity type. The third layer includes a third semiconductor layer of the first conductivity type.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 27, 2003
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventor: Fumihiko Hirose
  • Patent number: 6537887
    Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: March 25, 2003
    Assignee: Agere Systems Inc.
    Inventors: Yih-Feng Chyan, Chung Wai Leung, Yi Ma, Demi Nguyen
  • Publication number: 20030034549
    Abstract: The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive SFFs are connected, respectively, to the input pads and the output pads directly or via the combination circuit. In this configuration, the output pads and the input pads are connected to each other inside the chip to thereby form a test path.
    Type: Application
    Filed: July 9, 2002
    Publication date: February 20, 2003
    Inventor: Tatsunori Komoike
  • Publication number: 20020158308
    Abstract: A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and different collector widths. The buried layer of the second component has a larger layer thickness than that of the first component; exactly one epitaxial layer is provided. The different collector widths produced as a result thereof are influenced by the outdiffusion of the dopant of the buried layers by other substances.
    Type: Application
    Filed: May 13, 2002
    Publication date: October 31, 2002
    Inventors: Jakob Huber, Wolfgang Klein
  • Publication number: 20020153592
    Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.
    Type: Application
    Filed: April 19, 2002
    Publication date: October 24, 2002
    Inventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
  • Patent number: 6469365
    Abstract: A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more highly doped edge layer of the second conductivity type are disposed at the surface of the substrate and are isolated from one another by pn junctions. At least one of the wells is completely surrounded by an insulating well of the first conductivity type. The doping of the insulating well is higher than that of the substrate. A method for fabricating a semiconductor component is also provided.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: October 22, 2002
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Werner
  • Patent number: 6423590
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu
  • Patent number: 6265756
    Abstract: An electrostatic discharge protection device for reducing electrostatic discharge spikes on a signal line is disclosed. The electrostatic discharge protection device includes first and second contact regions formed in a semiconductor material such as a compound semiconductor substrate. A first terminal is electrically coupled between the signal line and the first contact region. A second terminal is electrically coupled between the second contact region and a sink such as ground. An isolation region is formed in the semiconductor material between the first and second contact regions. The isolation region may be an implant-damaged region of the semiconductor material. The electrostatic discharge protection device provides protection against electrostatic discharges for integrated circuit components, while adding only a small amount of parasitic capacitance to I/O lines, which is particularly important in RF signal processing circuitry.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: July 24, 2001
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Steven W. Brockett, Wesley C. Mickanin, Steven D. Bingham, Dennis A. Criss
  • Patent number: 6245609
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: June 12, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
  • Patent number: 6049118
    Abstract: A circuit built-in light-receiving element includes a buried diffusion layer of the second conductivity type, a buried diffusion layer of the first conductivity type, an epitaxial layer of the second conductivity type, a diffusion layer of the first conductivity type, and a signal processing circuit element. The buried diffusion layer of the second conductivity type is formed in a first region on a substrate of the first conductivity type. The buried diffusion layer of the first conductivity type is selectively formed in the buried diffusion layer of the second conductivity type. The epitaxial layer of the second conductivity type is formed on the buried diffusion layer of the first conductivity type. The buried diffusion layer of the first conductivity type and the epitaxial layer of the second conductivity type constitute a light-receiving element.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: April 11, 2000
    Assignee: NEC Corporation
    Inventor: Hiroki Nagano
  • Patent number: 6049131
    Abstract: A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Stephen Bruce Brodsky, Richard Anthony Conti, Seshadri Subbanna
  • Patent number: 6005284
    Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: December 21, 1999
    Assignee: Sony Corporation
    Inventors: Hirokazu Ejiri, Hiroyuki Miwa, Hiroaki Ammo
  • Patent number: 6005282
    Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: December 21, 1999
    Assignee: Analog Devices, Inc.
    Inventors: Jerome F. Lapham, Brad W. Scharf
  • Patent number: 5976940
    Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: November 2, 1999
    Assignee: Sony Corporation
    Inventors: Takayuki Gomi, Hiroaki Ammo
  • Patent number: 5939759
    Abstract: In a semiconductor device including a silicon substrate, an insulating layer on the silicon substrate, a silicon layer on the insulating layer, the silicon layer being weakly doped with impurities of a first conduction type, a base region extending into the silicon layer from the free surface thereof, the base region being doped with impurities of a second conduction type, an emitter region extending into the base region from the free surface thereof, the emitter region being heavily doped with impurities of the first conduction type, and at least one collector region extending into the silicon layer from the free surface thereof at a lateral distance from the base region, the collector region being doped with impurities of the first conduction type, a floating collector region is provided in the silicon layer between the insulating layer and the base region at a distance from the base region.
    Type: Grant
    Filed: June 21, 1997
    Date of Patent: August 17, 1999
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Torkel Bengt Arnborg
  • Patent number: 5915186
    Abstract: In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic base layer 12 to each other, and at least a part of a base layer 6 of the second bipolar transistor are formed simultaneously with each other, and then the link base layer 5 in a region where the intrinsic base layer 12 will be formed is removed by an etching treatment, and then by a selective epitaxial growth method, the intrinsic base layer 12 is formed in the region where the link base layer 5 is removed.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: June 22, 1999
    Assignee: Sony Corporation
    Inventor: Takayuki Gomi
  • Patent number: 5847440
    Abstract: An n-type epitaxial layer is formed on a main surface of a p-type silicon substrate. An n-type buried diffusion layer is formed extending in both the p-type silicon substrate and the n-type epitaxial layer. An n-type diffusion layer is formed in the surface of the n-type epitaxial layer, which is disposed above the n-type buried diffusion layer. A p-type diffusion layer is formed so as to surround side ends of the n-type diffusion layer. A p-type buried diffusion layer is formed so as to have a bottom face within the n-type buried diffusion layer and have side ends thereof inside side ends of the p-type diffusion layer. A collector region of a vertical pnp bipolar transistor consists of the p-type buried diffusion layer and the p-type diffusion layer. A p-type diffusion layer, which serves as an emitter region of the pnp bipolar transistor, is formed in the surface of the n-type diffusion layer.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: December 8, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Fumitoshi Yamamoto
  • Patent number: 5838048
    Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: November 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takehiro Hirai, Masahiro Nakatani, Mitsuo Tanaka, Akihiro Kanda
  • Patent number: 5798560
    Abstract: Buried N.sup.+ layers are formed in the surface of a substrate, on which first and second epitaxial layers are successively deposited. A vertical PNP transistor formed in the surface of the first epitaxial layer has a buried collector layer, a collector lead region, and a base contact region. The buried collector layer, the collector lead region, and the base contact region provide a buried anode layer, an anode lead region, and a cathode contact region, respectively, of a diode. The vertical PNP transistor and the diode are surrounded by N.sup.+ lead regions and the buried N.sup.+ layers.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: August 25, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Ohkawa, Toshiyuki Ohkoda
  • Patent number: 5641691
    Abstract: A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: June 24, 1997
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Eric N. Cartagena, Howard W. Walker
  • Patent number: 5523606
    Abstract: A BiCMOS semiconductor device includes a pair of p-channel and n-channel MOS field effect transistors, a hetero-junction bipolar transistor including an epitaxial base layer made of a first compound semiconductor, and a homo-junction bipolar transistor including a base layer made of a second semiconductor. The hetero-junction bipolar transistor is operated in a low collector current region less than a critical collector current value at which the hetero-junction bipolar transistor has the maximum value of a cutoff frequency thereof. The homo-junction bipolar transistor is operated in a high collector current region more than a critical collector current value at which the homo-junction bipolar transistor has the maximum value of a cutoff frequency thereof.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: June 4, 1996
    Assignee: NEC Corporation
    Inventor: Toru Yamazaki
  • Patent number: 5440153
    Abstract: A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capacitor. Each transistor has dual emitters, bases and collectors. Open field areas are reserved on the silicon substrate on the sides of the columns of cells. Formed in these open field areas are precise thin film silicon chromium resistors. Power planes are also routed in these open field areas. A ground plane is routed in the vicinity of the centrally-located capacitor. Standard analog circuits are personalized using two layers of metallization interconnects.
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: August 8, 1995
    Assignee: United Technologies Corporation
    Inventors: Barry J. Male, Douglas L. Anneser
  • Patent number: 5406106
    Abstract: A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: April 11, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takehiro Hirai, Masahiro Nakatani, Mitsuo Tanaka, Akihiro Kanda
  • Patent number: 5376822
    Abstract: A heterojunction type of compound semiconductor integrated circuit in which a PNP transistor has an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor, a P type second compound semiconductor limitedly arranged on a part of the substrate for functioning as an emitter of the PNP transistor, an N type third compound semiconductor arranged on both the second compound semiconductor and the substrate for functioning as a base of the PNP transistor, electrons being applied from the substrate to the third compound semiconductor, a P type fourth compound semiconductor limitedly arranged on a part of the N type third compound semiconductor, a P.sup.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: December 27, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Taguchi
  • Patent number: 5331198
    Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
    Type: Grant
    Filed: August 5, 1992
    Date of Patent: July 19, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5323054
    Abstract: In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: June 21, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5302848
    Abstract: A process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and a novel chip made by such a process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: April 12, 1994
    Assignee: Analog Devices, Inc.
    Inventors: Jerome F. Lapham, Brad W. Scharf
  • Patent number: 5254486
    Abstract: In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for the PNP transistor is self-aligned with the base region of the NPN transistor. All the defined regions are then doped to achieve a desired base region concentration. A next masking step forms a layer of resist over the base region, and the remainder of the previous masking pattern is retained to define the emitter and collector regions of the PNP transistor. P-type dopants are then implanted in the previously defined emitter and collector regions to form the heavily doped P++ emitter and collector regions of the PNP transistor. Thus, the P++ emitter and collector regions of the PNP transistor will be self-aligned with the P-type base region of the NPN transistor.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: October 19, 1993
    Assignee: Micrel, Incorporated
    Inventor: Martin J. Alter
  • Patent number: 5184203
    Abstract: A semiconductor device having a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on a major surface of the semiconductor subtrate, an isolation layer of the first conductivity type formed in the epitaxial layer and extending from a surface thereof to the major surface of the semiconductor substrate. The isolation layer divides the epitaxial layer into first, second, and third islands. The device further has two wells of the first conductivity type, formed in the first and second islands, respectively, and extending to the substrate, a charge transfer device having a back gate formed of the first well, an insulated-gate FET of the first conductivity type, having a back gate formed of the second island, an insulated-gate FET of the second conductivity type, having a back gate formed of the second well, and a bipolar transistor having a collector formed of the third island.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: February 2, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Taguchi
  • Patent number: RE35486
    Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: April 1, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Franco Bertotti, Paolo Ferrari