Abstract: A system, method and computer program product for composing persistent object instances that link resources across multiple, disparate systems. An example method includes associating resources with namespace-URLs and object instances. One of the namespace-URLs is designated as primary namespace-URL. A web-based object API is provided through which the object instance can be accessed. The web-based object API uses the primary namespace-URL as an identifier of the object instance.

Abstract: A device structure for a bipolar junction transistor includes a base layer made of a semiconductor material. An emitter is disposed on a first portion of the base layer. A dopant-containing layer is disposed on a second portion of the base layer. A hardmask is disposed on the base layer. The hardmask includes a window aligned with the second portion of the base layer. Deposits of the dopant-containing layer are limited to exposed surfaces of: the first portion that is disposed on a top surface of the base layer inside of the window.

Abstract: Methods for forming semiconductor devices herein may include forming a trench in a substrate layer, wherein a hardmask is disposed atop the substrate layer, and implanting the trench at an angle relative to a top surface of the hardmask. The method may further include forming an oxide layer within the trench, wherein a thickness of the oxide layer along a bottom portion of the trench is greater than a thickness of the oxide layer along an upper portion of the trench.

Abstract: A silicon island structure and a method of fabricating same are disclosed. The method includes: forming multiple first trenches in a silicon substrate; forming second trenches by partially filling some of the first trenches with an insulating material; depositing a protective layer over the silicon substrate and over the second trenches; removing the protective layer over bottoms of the second trenches and the insulating material under the second trenches, thereby exposing sidewalls of some first trenches; oxidizing portions of the silicon substrate between the exposed sidewalls of the first trenches to form an oxide layer; removing the protective layer covering sidewalls of the second trenches; and filling the second trenches with an isolating material to form isolations, wherein portions of the silicon substrate between the isolations define silicon islands. This method enables the formation of silicon islands at desired locations with reduced process complexity and cost.

Abstract: A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode.

Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended.

Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.

Abstract: A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.

Abstract: The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Abstract: A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region.

Abstract: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region.

Abstract: A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a first power line (such as Vdd), a second power line (such as Vss) and a bond pad of an integrated circuit respectively. The diode has an n electrode and a p electrode electrically connected to the first power line and the bond pad respectively.

Abstract: Methods for fabricating an assembly having functional blocks coupling to a substrate. The method includes providing the substrate with receptor sites wherein each of the receptor sites is designed to couple to one of the functional blocks. Electrodes are coupled to the substrate. The electrodes cover the receptor sites such that portions of the receptor sites are coated with the electrodes. Applying a voltage source to the electrodes using a first electrical circuit such that each electrode has a voltage different from another electrode. The electrodes form an electric field. The functional blocks having electronic devices and being in a slurry solution are dispensed over the substrate. Each functional block is fabricated out of materials having a high dielectric constant such that said functional blocks are attracted to the higher field strength regions and are guided to the receptor sites.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A thermal oxidation process is used to fill trenches with an oxide; however, the oxidation process consumes some of the silicon. The embodiments herein advantageously apply this tendency for the oxidation process to consume silicon so as to convert all the silicon substrate material between the multiple trenches into an oxide. Therefore, because all of the silicon between the multiple trenches is consumed by the oxidation process, the multiple smaller trenches are combined into a single larger trench filled with the oxide.

Abstract: A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Abstract: A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: A method of manufacturing a semiconductor component includes: providing a semiconductor substrate (210, 510); forming a trench (130, 430) in the semiconductor substrate to define a plurality of active areas separated from each other by the trench; forming a buried layer (240, 750) in the semiconductor substrate underneath a portion of the trench, where the buried layer is at least partially contiguous with the trench; after forming the buried layer, depositing an electrically insulating material (133, 810) in the trench; forming a collector region (150, 950) in one of the plurality of active areas, where the collector region forms a contact to the buried layer; forming a base structure over the one of the plurality of active areas; and forming an emitter region over the one of the plurality of active areas.

Abstract: The gist of the present invention is as follows: In a monolithic microwave integrate circuit (MMIC) using a heterojunction bipolar transistor (HBT), via holes are respectively formed from the bottom of the MMIC for the emitter, base and collector. Of the via holes, one is located so as to face the HBT. The respective topside electrodes for the other via holes located so as not to face the HBT are provided in contact with the MMIC substrate.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the BJT to improve Bvceo. The inclusion of the scattering centers allows the width of the collector region WCD (90) to be reduced leading to an improvement in Ft/Fmax.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.

Abstract: A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.

Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.

Abstract: In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film in an SOI substrate with an electrically conductive film is utilized for an emitter and/or a collector, whereby a bipolar transistor is formed through a simple process.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: The present invention provides a standard cell which can reduce an effective cell size and improve an integration degree of a semiconductor integrated circuit. The standard cell includes a plurality of MOS transistors formed on a semiconductor substrate. Then, a plurality of standard cells are adjacent to each other in upper, lower, left and right directions, and constitute the semiconductor integrated circuit. The present invention is intended to reduce the effective cell size in such a way that a source region of a MOS transistor connected to a power supply voltage or a ground voltage is shared between cells adjacent to each other. Also, even if the source region is not shared, a source region of one cell in the cells adjacent to each other is arranged in an empty space region of the other cell in such a way that it bestrides between the cells adjacent to each other.

Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Abstract: A semiconductor device is disclosed, together with a fabricating method therefor. The semiconductor device has an etch barrier structure, made with SiN or SiON, which is formed on an element-isolating region alongside an active region. Although there is an alignment error which causes the element-isolating region to be exposed, the etch barrier structure protects the element-isolating region from being etched when carrying out the etching processes for contact holes in a semiconductor memory cell. Thus, while preventing the deterioration of element-isolation properties, the etch barrier structure can affords a larger allowable alignment error in the etching processes for contact holes, so it is possible to make a small active region and thus, highly integrate semiconductor devices.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A manufacturing method for semiconductor components is disclosed which will allow better precision in the definition of the doped areas of the components and the separation of differently doped areas. A selectively shaped area of, for example, polysilicon, defining the area or areas to be doped, is deposited on the component before the masks are applied. This makes the fitting of the masks less critical, as they only have to be fitted within the area of the polysilicon layer. In this way an accuracy of 0.1 .mu.m or better can be achieved.

Abstract: A compound semiconductor device having a mesa type heterojunction bipolar transistor comprises a collector layer of first conductivity type having a collector breakdown voltage of a predetermined magnitude, a base layer of second conductivity type formed on the collector layer, an emitter layer of first conductivity type formed on the base layer, and a subcollector layer of first conductivity formed in a region remote laterally from an edge of the base layer to be connected to the collector layer.

Abstract: The non-volatile semiconductor memory device is formed on a silicon substrate and comprises a plurality of semiconductor active regions defined by a plurality of element isolation regions, a source region and a drain region formed in each of the semiconductor active regions, a charge storage layer which capacitively couples to the semiconductor active region between the source region and the drain region, and a control gate which capacitively couples to the charge storage layer through a second gate insulation film, wherein the second gate insulation film is left extending from the upper surface portion of the element isolation region which lies under the control gate to the upper surface portion of the element isolation region other than the upper surface portion of the element isolation region lying under the control gate.

Abstract: A semiconductor integrated circuit having a lateral bipolar transistor, is fabricated in a manner compatible with sub-micron CMOS processing. A base contact structure is formed over a bipolar active area, in essentially direct contact to a portion of the upper surface of the active region, essentially concurrent to the formation of a gate electrode on a gate dielectric layer in a CMOS active area. Sidewall spacers, adjacent the base contact region, are formed and a base region formed under the base contact structure using an oblique angle implantation. Emitter region and collector contact regions are formed concurrent with CMOS source and drain regions. An optional, oblique angle collector implant can be performed where desired.

Abstract: A semiconductor device having an epitaxial layer of one conductivity type formed on a semiconductor substrate of the other conductivity type, a base region of the other conductivity type formed on the epitaxial layer to extend from a surface of the epitaxial layer to a predetermined depth, the base region including an intrinsic base region and an external base region, an emitter region of the one conductivity type formed in the intrinsic base region, and a pedestal collector region of the one conductivity type formed in a portion of the epitaxial layer which is immediately under the base region to correspond thereto, wherein the pedestal collector region comprises a plurality of layers of pedestal collector regions which have an impurity concentration that changes in a direction of depth of the substrate and which are sequentially arranged in the direction of depth of the substrate.

Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.

Abstract: Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.

Abstract: A process for fabricating a bipolar junction transistor by forming a trench in a silicon substrate. A lightly-doped base region is formed adjacent to the sidewalls of the trench, and a heavily-doped base region is formed under the bottom of the trench. Silicon oxide layers are formed along the sidewalls and bottom of the trench with a contact window provided to expose part of the lightly-doped base region. A polysilicon layer is formed in the trench, and is heavily doped by a dopant which in turn diffuses into the lightly-doped base region through the contact window to form an emitter region. A collector region is formed in the upper surface of the lightly-doped base region.

Abstract: This invention pertains to a lateral bipolar transistor comprising an emitter, a base and a collector. The transistor exhibits improved function and overall size reduction, due to the base and emitter structure. An island forms both the base and emitter regions in the transistor structure with the base region being above the collector region, below the emitter region, and surrounded by a dielectric region. The emitter is surrounded by emitter isolation walls, which are formed approximately 0.2 microns above the plane of the dielectric region, such that any manufacturing variances will not cause the emitter isolation walls to contact the dielectric region and pinch-off the base region from the base junction region. This structure also allows the size of the base-emitter junction to be decreased without increasing the parasitic characteristics of the transistor.