Lateral Bipolar Transistor Structure Patents (Class 257/557)
  • Patent number: 10361189
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench electrode provided in a trench, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate, in which the semiconductor substrate includes a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, a third semiconductor layer provided over the second semiconductor layer, a fourth semiconductor layer provided below the MOS electrode, and one and the other of fifth semiconductor layers provided on both sides of the fourth semiconductor layer, and in which the semiconductor device further includes a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: July 23, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Ryo Kanda
  • Patent number: 10224402
    Abstract: In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BVCEO) and BJT's gain, are improved by forming a graded collector contact region with lower doping levels toward the base contact.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: March 5, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Natalia Lavrovskaya, Alexei Sadovnikov
  • Patent number: 9786656
    Abstract: A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Xuefeng Liu, Junli Wang
  • Patent number: 9773894
    Abstract: A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 9478630
    Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
  • Patent number: 9472657
    Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: October 18, 2016
    Assignee: Fitipower Integrated Technology, Inc.
    Inventor: Chih-Nan Cheng
  • Patent number: 9425298
    Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fabio Carta, Daniel C. Edelstein, Stephen M. Gates, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 9159816
    Abstract: Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David L. Harame, Qizhi Liu
  • Patent number: 9029955
    Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 12, 2015
    Assignees: Commissariat á l'énergie atomique et aux énergies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 8962436
    Abstract: A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Ghavam G. Shahidi, Jeng-Bang Yau
  • Patent number: 8927380
    Abstract: A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning
  • Patent number: 8916951
    Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 23, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, François Hébert
  • Publication number: 20140367829
    Abstract: An ESD protection apparatus comprises an n-type substrate with a first doping density, a low voltage n-type well in the substrate, a low voltage p-type well in the substrate, a first n-type semiconductor region over the low voltage n-type well and a second n-type semiconductor region over the low voltage p-type well, wherein the first semiconductor region and the second semiconductor region are separated by a first isolation region.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 18, 2014
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Publication number: 20140353757
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Application
    Filed: July 3, 2014
    Publication date: December 4, 2014
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Patent number: 8896021
    Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chung-I Huang, Pao-An Chang, Ming-Tsung Lee
  • Patent number: 8853043
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Patent number: 8853825
    Abstract: An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8816418
    Abstract: A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyongsoo Kim, Eunkee Hong, Kwangtae Hwang
  • Patent number: 8791500
    Abstract: A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 29, 2014
    Assignee: DENSO CORPORATION
    Inventors: Youichi Ashida, Shigeki Takahashi
  • Patent number: 8786024
    Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 22, 2014
    Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8710650
    Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukchul Bang, Kwangjin Moon, Byung Lyul Park, Dosun Lee, Deok-Young Jung, Gilheyun Choi
  • Patent number: 8618606
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: December 31, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Patent number: 8569866
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 29, 2013
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8569865
    Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 8552530
    Abstract: A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: October 8, 2013
    Assignee: Amazing Microelectronics Corp.
    Inventors: Kun-Hsien Lin, Zi-Ping Chen, Che-Hao Chuang, Ryan Hsin-Chin Jiang
  • Patent number: 8536701
    Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: September 17, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Ra-Min Tain, Ming-Ji Dai, John H. Lau
  • Patent number: 8502344
    Abstract: A lateral high-breakdown voltage semiconductor device is provided in which the breakdown voltages of elements as a whole are improved, while suppressing increases in cell area. A track-shape gate electrode surrounds a collector electrode extending in a straight line, a track-shape emitter electrode surrounds the gate electrode, and a track-shape first isolation trench surrounds the emitter electrode. A second isolation trench surrounds the first isolation trench. The region between the first isolation trench and the second isolation trench is an n-type isolation silicon region. The isolation silicon region is at the same potential as the emitter electrode. In the cross-sectional configuration traversing the gate electrode, the depth of the p base region in an interval corresponding to an arc-shape portion of the gate electrode is shallower than the depth of the p base region in an interval corresponding to a straight-line portion of the gate electrode.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: August 6, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hong-fei Lu
  • Patent number: 8441084
    Abstract: A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Wilfried E. Haensch, Tak H. Ning
  • Patent number: 8431450
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Patent number: 8410572
    Abstract: A base contact connection, an emitter structure and a collector structure are arranged on an n-layer, which can be provided for additional npn transistors. The collector structure is arranged laterally to the emitter structure and at least one of the emitter and collector comprises a Schottky contact on a surface area of the n-layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 2, 2013
    Assignee: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Publication number: 20130075829
    Abstract: An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Ming-Fang LAI
  • Publication number: 20130075854
    Abstract: An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Publication number: 20130075863
    Abstract: An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8384183
    Abstract: An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 26, 2013
    Assignee: Allegro Microsystems, Inc.
    Inventors: Harianto Wong, William P. Taylor, Ravi Vig
  • Patent number: 8334579
    Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping Chun Yeh, Der-Chyang Yeh, Chih-Ping Chao
  • Publication number: 20120286396
    Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 15, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventor: Edward Coyne
  • Patent number: 8304858
    Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: November 6, 2012
    Assignee: Panasonic Corporation
    Inventors: Teruhisa Ikuta, Yoshinobu Sato
  • Patent number: 8299532
    Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Tai-Hsiang Lai, Kuei-Chih Fan, Tien-Hao Tang
  • Patent number: 8283696
    Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 8278736
    Abstract: An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: October 2, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Chia-Wei Hung, Shu-Ling Chang, Hwa-Chyi Chiou, Yeh-Jen Huang
  • Patent number: 8264038
    Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu, Xinfen Chen
  • Publication number: 20120168906
    Abstract: An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region.
    Type: Application
    Filed: April 21, 2011
    Publication date: July 5, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Yu Kuo, Jam-Wem Lee, Yi-Feng Chang
  • Publication number: 20120133024
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Prechtl, Andreas Peter Meiser, Thomas Ostermann
  • Patent number: 8138575
    Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: March 20, 2012
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Publication number: 20120043643
    Abstract: An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.
    Type: Application
    Filed: March 7, 2011
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-ryul Chang, Oh-kyunm Kwon
  • Patent number: 8115280
    Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Shuo-Mao Chen, Chin-Wei Kuo, Sally Liu
  • Patent number: 8093644
    Abstract: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: January 10, 2012
    Assignee: Internationl Business Machines Corporation
    Inventor: Haining S. Yang
  • Patent number: 8049307
    Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 1, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Shang-Hui Tu, Jui-Chun Chang, Chen-Wei Wu
  • Patent number: 8030167
    Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, Bradley A. Orner, Jay S. Rascoe, David C. Sheridan, Stephen A. St. Onge