Including Additional Component In Same, Non-isolated Structure (e.g., Transistor With Diode, Transistor With Resistor, Etc.) Patents (Class 257/577)
  • Patent number: 10777409
    Abstract: A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 15, 2020
    Inventor: L. Pierre de Rochemont
  • Patent number: 10446409
    Abstract: An interlayer insulating film is dry etched using a CHF3 gas and by using, as a mask, a resist film having a first opening and a second opening that is wider than the first opening, thereby forming a first contact hole of a predetermined depth in the first opening and forming a second contact hole in the second opening. The gas in a furnace is switched to a C4F8 gas and the first contact hole is embedded with a polymer by the C4F8 gas. The gas in the furnace is switched to a CHF3 gas. With the first contact hole protected by the polymer, the interlayer insulating film is dry etched using the same resist film as a mask, making a depth of the second contact hole a predetermined depth deeper than that of the first contact hole. Thereafter, the resist film and the polymer are removed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kuneshita
  • Patent number: 10236237
    Abstract: Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenji Sasaki
  • Patent number: 10181466
    Abstract: An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Ming-Yin Lee, Wen-Tsung Huang
  • Patent number: 10026815
    Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1ยท1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rick L. Wise, Hiroshi Yasuda
  • Patent number: 9961764
    Abstract: A via conductor connected to a mounting electrode near a corner portion of a circuit substrate is provided in a position in a corresponding mounting electrode, located closer to the center of the circuit substrate. Thus, concentration of a stress in a portion of the via conductor is effectively reduced, and a break, a chip, or a crack is prevented from occurring to the circuit substrate. Even if the portion located closer to the corner portion of the mounting electrode is peeled from the circuit substrate, the electrical characteristics of the circuit module are secured because disconnection between the corresponding mounting electrode and the via conductor is prevented.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: May 1, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hiromichi Kitajima
  • Patent number: 9831330
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device having a deep charge-balanced structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes a control trench extending through an inversion region having the second conductivity type into the drift region, and bordered by a cathode diffusion having the first conductivity type. In addition, the device includes a deep sub-trench structure situated under the control trench. The deep sub-trench structure includes one or more first conductivity regions having the first conductivity type and one or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the one or more second conductivity regions configured to substantially charge-balance the deep sub-trench structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Patent number: 9488776
    Abstract: A method for fabricating electronic and photonic devices on a semiconductor substrate using complementary-metal oxide semiconductor (CMOS) technology is disclosed. A substrate is initially patterned to form a first region for accommodating electronic devices and a second region for accommodating photonic devices. The substrate within the first region is thicker than the substrate within the second region. Next, an oxide layer is formed on the substrate. The oxide layer within the first region is thinner than the oxide layer within the second region. A donor wafer is subsequently placed on top of the oxide layer. The donor substrate includes a bulk silicon substrate, a sacrificial layer and a silicon layer. Finally, the bulk silicon substrate and the sacrificial layer are removed from the silicon layer such that the silicon layer remains on the oxide layer.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 8, 2016
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Craig M. Hill, Andrew T S Pomerene
  • Patent number: 9379257
    Abstract: An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: June 28, 2016
    Assignee: Infineon Technologies AG
    Inventor: Jakob Huber
  • Patent number: 9356127
    Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: May 31, 2016
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Hsiao Tsai, Hsiu-Chen Chang, Shinichiro Takatani, Cheng-Kuo Lin
  • Patent number: 9337171
    Abstract: A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 10, 2016
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 9310261
    Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: April 12, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ricardo P. Coimbra, Edevaldo Pereira Da Silva, Jr., Pedro B. Zanetta
  • Patent number: 9123768
    Abstract: A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 1, 2015
    Inventor: L. Pierre de Rochemont
  • Patent number: 9074943
    Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, Jr., Pedro B. Zanetta
  • Patent number: 9035427
    Abstract: Provided are metal-semiconductor convergence electric circuit devices. The device includes a semiconductor device, a metal resistor exhibiting resistance increased with an increase in temperature thereof, and an interconnection line connecting the semiconductor device with the metal resistor in series and having a resistance lower than that of the metal resistor. The semiconductor device is configured to exhibit resistance decreased with an increase in temperature thereof and compensate the resistance increase of the metal resistor.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: May 19, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Tak Kim, Bongjun Kim
  • Patent number: 9029952
    Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: May 12, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
  • Publication number: 20150097269
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device includes: a conductive layer; a P-type semiconductor substrate, which is formed on the conductive layer; an N-type buried layer, which is formed on the semiconductor substrate; a P-type lightly doped layer, which is formed on the buried layer; a P-type cap region, which is formed on the lightly doped layer; and an N-type reverse region, which is formed on the cap region, wherein a Zener diode includes the reverse region and the cap region, and an NPN bipolar junction transistor (BJT) includes the reverse region, the cap region, the lightly doped layer and the buried layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Wu-Te Weng
  • Patent number: 8975663
    Abstract: There is provided a semiconductor device such that it is possible to average the temperatures of a plurality of semiconductor chips simply by providing gate resistors. The semiconductor device includes a semiconductor module wherein a plurality of circuit substrates on which are mounted one or more semiconductor chips having a gate terminal and a gate resistor connected to the gate terminal are disposed in parallel, wherein the disposition distance of the gate resistor from the semiconductor chip is set based on the temperature of the semiconductor chip.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 10, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yujin Okamoto
  • Publication number: 20150054133
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
    Type: Application
    Filed: October 1, 2014
    Publication date: February 26, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Yogesh LUTHRA, Serguei OKHONIN, Mikhail NAGOGA
  • Patent number: 8946038
    Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8941181
    Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
  • Patent number: 8941161
    Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita
  • Publication number: 20150001679
    Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kouichi SAWAHATA
  • Publication number: 20140367783
    Abstract: An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink region disposed vertically below the collector region, and a burier layer protruding horizontally further than the sink region under the sink region.
    Type: Application
    Filed: February 24, 2014
    Publication date: December 18, 2014
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Kyong Jin HWANG, Jin Seop SHIM, Jae Hyun LEE
  • Publication number: 20140367830
    Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rouying Zhan, Chai Ean Gill
  • Publication number: 20140353799
    Abstract: An ESD transistor is provided. The ESD transistor includes a collector region on a substrate, a base contact region on the substrate, an emitter region spaced apart from the base contact region, a sink region disposed vertically below the collector region, and a buried layer disposed horizontally under the sink region.
    Type: Application
    Filed: January 28, 2014
    Publication date: December 4, 2014
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Kyong Jin HWANG
  • Patent number: 8896024
    Abstract: Provided is an electrostatic discharge (ESD) protection structure including a first and a second well region adjacent to each other, a first and a second doped region disposed in the first well region, a fourth and a fifth doped region disposed in the second well region, and a third doped region disposed in the first region and extending into the second well region. The second doped region is disposed between the first and the third doped regions, forming a diode with the first doped region, forming, together with the first well region and the second well region, a first bipolar junction transistor (BJT) electrically connecting to the diode, and having no contact window disposed thereon. The fourth doped region is disposed between the third and the fifth doped regions, forming a second BJT with the second well region and the first well region.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Chun Chen, Li-Cih Wang, Lu-An Chen, Tien-Hao Tang
  • Patent number: 8860139
    Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Sawahata
  • Patent number: 8859386
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
  • Patent number: 8853790
    Abstract: An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20140291808
    Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 2, 2014
    Inventors: Jens Schneider, Kai Esmark, Martin Wendel
  • Publication number: 20140247527
    Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Seiji OTAKE, Yasuhiro TAKEDA, Yuta MIYAMOTO
  • Patent number: 8816388
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 8810004
    Abstract: A resistor-equipped transistor includes a package that provides an external collector connection node (114, 134), an external emitter connection node (120, 140) and an external base connection node (106, 126). The package contains a substrate upon which a transistor (102, 122), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (118, 138), an internal emitter (120, 140) and an internal base (116, 136) with the first resistor (104, 124) being electrically connected between the internal base and the external base connection node and the second resistor (108, 128) being electrically connected between the internal base and the internal emitter.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: August 19, 2014
    Assignee: NXP, B.V.
    Inventors: Stefan Bengt Berglund, Steffen Holland, Uwe Podschus
  • Patent number: 8803276
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
  • Publication number: 20140210053
    Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: ROBERT STEINHOFF, Jonathan Brodsky
  • Patent number: 8779551
    Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
  • Patent number: 8772837
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11. An emitter electrode 31A and a collector electrode 31B are formed in the open region 21 and are composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 8, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8735955
    Abstract: A grounding system for a semiconductor module of a variable speed drive includes a first conductive layer, a second conductive layer; a substrate disposed between the first conductive layer and the second conductive layer; and a base attached to the second conductive layer, the base being connected to earth ground via a grounding harness. The first conductive layer is in electrical contact with the semiconductor module and the substrate, and electrically insulated from the second conductive layer by the substrate. The second conductive layer is in electrical contact with the substrate and disposed between the substrate and the base in electrical communication with an earth ground. The first conductive layer, the substrate and the second conductive layer form a capacitance path between the semiconductor module and the base as well as electrical conductors and the base for reduction circulating currents within the semiconductor module.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 27, 2014
    Assignee: Johnson Controls Technology Company
    Inventors: Konstantin Borisov, Michael S. Todd, Shreesha Adiga-Manoor, Ivan Jadric
  • Publication number: 20140124894
    Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 8, 2014
    Applicant: IMEC
    Inventors: Geert Hellings, Mirko Scholz, Dimitri Linten
  • Patent number: 8686513
    Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 1, 2014
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 8664697
    Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Meguro, Jiro Wada, Yoshihiko Moriya
  • Patent number: 8643146
    Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Uemura
  • Publication number: 20130334665
    Abstract: A semiconductor device is disclosed with a protection device formed of a parasitic bipolar transistor, a parasitic diode and a parasitic resistance and operated at a lowered operating voltage to be capable of improving a blocking capability against an over voltage. The impurity concentration in a semiconductor layer as the base of a parasitic bipolar transistor is lower compared with the impurity concentration of a semiconductor layer of the same conduction type arranged adjacently to the semiconductor layer as the base and to be the anode of a parasitic diode. The lowered impurity concentration is determined to be the concentration for making the parasitic bipolar transistor have a snapback phenomenon occur.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 19, 2013
    Inventor: Osamu SASAKI
  • Patent number: 8610241
    Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8604514
    Abstract: The present teachings provides a bipolar semiconductor device comprising: a main cell region consisting of a trench gate type element region; and a sense cell region including a planar gate type element region.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hiroaki Tanaka
  • Patent number: 8604590
    Abstract: A bipolar transistor structure with multiple electrodes configured to include an enhanced base capacitive element. Alternatively, a transistor with an integrated light emitting capacitive (LEC) element at the source or drain of the transistor. The transistor may be a stand alone transistor for usage in discrete applications, or may be implemented in a pixel circuit used in a display apparatus. In the pixel circuit embodiment, driver circuitry causes appropriate charging and discharging of the LEC elements of respective pixels to provide a desired display. In one alternative, a transistor may be configured to have multiple LEC elements integrated therewith, to provide respective different colors used in forming a display.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: December 10, 2013
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Leonard D. Nicoletti
  • Publication number: 20130320499
    Abstract: By configuring an ESD protection element of an NPN transistor (101), it is possible to reduce the area of the ESD protection element and reduce the voltage in a region in which the current increases sharply, and thus possible to increase ESD tolerance. Also, it is possible to provide a highly reliable semiconductor device wherein it is possible to flatten and smooth the surface of an upper layer pad electrode (16) by dividing a pad electrode (8) into a two-layer structure sandwiching an interlayer insulating film (15), and possible to increase the junction strength of a bonding wire, and suppress damage to underlying silicon layers when bonding.
    Type: Application
    Filed: December 1, 2011
    Publication date: December 5, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Taichi Karino
  • Patent number: 8569866
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 29, 2013
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8569780
    Abstract: A trench semiconductor power device integrated with a Gate-Source and a Gate-Drain clamp diodes without using source mask is disclosed, wherein a plurality source regions of a first conductivity type of the trench semiconductor device and multiple doped regions of the first conductivity type of the clamp diodes are formed simultaneously through contact open areas defined by a contact mask.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 29, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh