Abstract: Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

Abstract: An organic EL device includes an organic EL emitter that emits blue light and a blue color filter through which the light emitted from the organic EL emitter passes. The blue color filter contains a coloring material selected from the group consisting of a methine dye, a copper-phthalocyanine pigment, and a mixture of a copper-phthalocyanine pigment and a dioxazine pigment. The chromaticity of the light, the light that has passed through the blue color filter after emitted from the organic EL emitter, is in the range defined by lines connecting three chromaticity coordinates (0.140, 0.080), (0.136, 0.040), and (0.118, 0.070) on the CIE chromaticity diagram.

Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.

Abstract: An electrostatic discharge (ESD) protection clamp (21, 21?, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21?, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (?Vt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21?, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

Abstract: A heterojunction bipolar transistor (HBT) device and system having electrostatic discharge ruggedness, and methods for making the same, are disclosed. An HBT device having electrostatic discharge ruggedness may include one or more emitter fingers including an emitter layer, a transition layer formed over the emitter layer, and an emitter cap layer formed over the transition layer.

Abstract: A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.

Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Abstract: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.

Abstract: A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device.

Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.

Abstract: A semiconductor apparatus comprises a plurality of transistor devices including a control terminal being inputted with a control signal and a first and a second terminals that a current flows therein according to the control signal, and a plurality of substrate conductive portions each formed in a region different from a region where the plurality of transistor devices are formed therein, wherein the transistor devices are connected to the substrate conductive portions, and each of the substrate conductive portion includes a semiconductor layer separated from other substrate conductive portions.

Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V).

Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

Abstract: A high-frequency switching transistor comprises a collector area, which has a first conductivity type, a first barrier area bordering on the collector area, which has a second conductivity type which differs from the first conductivity type, and a semiconductor area bordering on the first barrier area, which has a dopant concentration which is lower than a dopant concentration of the first barrier area. Further, the high-frequency switching transistor has a second barrier area bordering on the semiconductor area, which has a first conductivity type, as well as a base area bordering on the second barrier area, which has a second conductivity type. Additionally, the high-frequency switching transistor comprises a third barrier area bordering on the semiconductor area, which has the second conductivity type and a higher dopant concentration than the semiconductor area. Further, the high-frequency switching transistor has an emitter area bordering on the third barrier area, which has the first conductivity type.

Abstract: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT device to the emitter electrode (12) are provided. The first emitter terminal (151) and the second emitter terminal (152) are individually connected to the emitter terminal (12) by wire bonding.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.

Abstract: A method of manufacturing a semiconductor component includes: providing a semiconductor substrate (210, 510); forming a trench (130, 430) in the semiconductor substrate to define a plurality of active areas separated from each other by the trench; forming a buried layer (240, 750) in the semiconductor substrate underneath a portion of the trench, where the buried layer is at least partially contiguous with the trench; after forming the buried layer, depositing an electrically insulating material (133, 810) in the trench; forming a collector region (150, 950) in one of the plurality of active areas, where the collector region forms a contact to the buried layer; forming a base structure over the one of the plurality of active areas; and forming an emitter region over the one of the plurality of active areas.

Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.

Abstract: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT device to the emitter electrode (12) are provided. The first emitter terminal (151) and the second emitter terminal (152) are individually connected to the emitter terminal (12) by wire bonding.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises an emitter. The heterojunction bipolar transistor further comprises a first emitter cap comprising a first high-doped layer, a low-doped layer, and a second high-doped layer, where the first high-doped layer is situated on the emitter, the low-doped layer is situated on the first high-doped layer, and the second high-doped layer is situated on the low-doped layer. The first high-doped layer, the low-doped layer, and the second high-doped layer form an emitter ballast resistor. According to this exemplary embodiment, the low-doped layer has a thickness and a dopant concentration level such that the resistance of the low-doped layer is substantially independent of the dopant concentration level, but corresponds to the thickness of the low-doped layer.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A semiconductor component includes a first layer and at least one adjacent semiconductor layer or metallic layer, which forms a rectifying junction with the first layer. Further semiconductor layers and metallic layers are provided for contacting the component. Insulating or semi-insulating structures are introduced into the first layer in a plane parallel to the rectifying junction. These structures are shaped like dishes with their edges bent up towards the rectifying junction. A method of producing such a semiconductor component is also provided.

Abstract: A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector contact for coupling to the collector terminal is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate, a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor, an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region. the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.

Abstract: A power semiconductor device has an integral source/emitter ballast resistor. The gate has partial gate structures spaced apart from each other. Emitter resistors are provided beneath sidewall spacers on the ends of the gate structures. The emitter resistors have little effect on the threshold voltage under normal operating conditions, but rapidly saturate the device during short circuit conditions. This in turn increases the short circuit withstand capability o the device.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements.

Abstract: A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.

Abstract: A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector terminal for coupling to the collector contact is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: A compound semiconductor device having a mesa type heterojunction bipolar transistor comprises a collector layer of first conductivity type having a collector breakdown voltage of a predetermined magnitude, a base layer of second conductivity type formed on the collector layer, an emitter layer of first conductivity type formed on the base layer, and a subcollector layer of first conductivity formed in a region remote laterally from an edge of the base layer to be connected to the collector layer.

Abstract: A ballasted transistor structure reduces thermal runaway. A heterojunction bipolar junction transistor array includes a plurality of transistors, each having an emitter, a base and a collector. Each of the bases is an alloy of silicon and germanium and each of the collectors and emitters is silicon. A ballast resistor, of doped silicon, that prevents thermal runaway, is electrically connected to each of the collectors.

Abstract: An integrated device in an emitter-switching configuration comprises a first bipolar transistor having a base region, an emitter region, and a collector region, a second transistor having a charge-collection terminal connected to an emitter terminal of the first transistor, and a quenching element having a terminal connected to a base terminal of the first transistor. The quenching element is formed within the base region or the emitter region of the first transistor.

Abstract: A heterojunction bipolar transistor is provided with a ballast resistor layer in an emitter layer which prevents the current amplification factor .beta. from decreasing. The n-GaAs carrier supply layer having a specified carrier concentration is formed between the ballast resistor layer and the n-AlGaAs layer.

Abstract: A hetero-junction bipolar transistor having high reliability wherein a ballast resistance is exactly controlled and deterioration in current stability is eliminated. A GaAs ballast resistor layer is provided in a hetero-junction bipolar transistor having a GaAs emitter layer, an InGaP spacer layer, and a GaAs base layer, preventing a notch from being formed in the conduction band at the interface of the emitter layer and the ballast resistor layer, exactly controlling the ballast resistance. The AlGaAs layer is prevented from trapping impurities and the current stability is prevented from deteriorating.

Abstract: A semiconductor device provided with a planar bipolar transistor and a built-in ingredient acting as an element to protect the bipolar transistor from an external surge voltage e.g. an electrostatic surge voltage and the like, is provided with a planar bipolar transistor further provided with a doped region having a conductivity opposite to that of a semiconductor substrate in which the foregoing planar bipolar transistor is produced, the doped region being produced along the top surface of the semiconductor substrate at a location close to the bipolar transistor, and the emitter of the bipolar transistor being connected the doped region and a fixed potential (V.sub.EE) or the ground potential, whereby the operation speed of a circuit including the transistor is not reduced by potential parasitic capacitors which otherwise accompany the built-in ingredients produced to protect the transistor from an external surge voltage e.g. an electrostatic surge voltage and the like.

Abstract: In order to avoid thermal runaway bipolar transistors, emitters are provided with ballast resistors. Elongate ballast resistors may be used, part of the lengths being connected for obtaining suitable resistance and design variability. The emitters are split up into a plurality of emitter portions, each with a separate emitter ballast resistor. The collector and base are correspondingly split up. The transistor is split up into unit cells, each comprising an emitter, a ballast resistor, a base, and a collector, which are respectively connected via respective common leads. This structure may advantageously be realized in a SOI technique, the galvanic isolation enabling unproblematic mixing of digital and analog and power devices in the same chip.

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

Abstract: A transistor component is suited for controlling large currents, even given high frequencies. The transistor component includes integrated emitter resistors which are arranged between partial-emitter regions and emitter-metal contacts. The integrated emitter resistors cause a stabilized, uniform current distribution both over the various partial-emitter regions, and within the partial-emitter regions, and bring about an improved current carrying capacity, as well as improved high-frequency properties, particularly in view of the finite magnitude of the extrinsic base resistance.

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.

Abstract: An RF power transistor having improved thermal balance characteristics includes a first emitter electrode and a base electrode formed on a silicon die, each having a multiplicity of parallel electrode fingers. A second emitter electrode is formed over the base electrode, and is electrically connected to the first emitter electrode. Ballast resistors are formed in a substantially evenly spaced manner on each side the silicon die, in series with at least some of the electrode fingers of the first emitter electrode and in series of at least some of the electrode fingers of the second emitter electrode.

Abstract: A bipolar transistor circuit element includes a semiconductor substrate; successively disposed on the substrate, a base layer, an emitter layer, and a collector layer; a bipolar transistor formed from parts of the collector, base, and emitter layers and including a base electrode electrically connected to the base layer and a base electrode pad for making an external connection to the base layer; a base ballasting resistor formed from a part of the base layer isolated from the bipolar transistor and electrically connecting the base electrode to the base electrode pad; and a base parallel capacitor connected in parallel with the base ballasting resistor wherein the base parallel capacitor includes part of the base input pad, a dielectric film disposed on part of the base electrode pad, and a second electrode disposed on the dielectric layer opposite the base electrode pad and electrically connected to the emitter electrode of the bipolar transistor.

Abstract: An inductive driver circuit (10) has a driver transistor (11) that is used for driving loads. An input protection device (13) and a voltage suppression device (12) assist in protecting the transistor (11). The circuit (10), including the driver transistor (11) and the input protection device (13), are formed in a common collector region.

Abstract: Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.