With Enlarged Emitter Area (e.g., Power Device) Patents (Class 257/578)
  • Patent number: 10211329
    Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Hyeongnam Kim, Mohamed Imam, Alain Charles, Jianwei Wan, Mihir Tungare, Chan Kyung Choi
  • Patent number: 9917088
    Abstract: A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion, a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source have concave surfaces, a second gate structure over the second portion and a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source have the concave surfaces.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yuan Wu, Yen-Po Lin, Yu-Shan Lu, Che-Yuan Hsu
  • Patent number: 9911837
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two parallel bars connected by a cross-bar. Two elongated emitter electrodes are formed respectively on the two parallel bars of the “H” shaped emitter. The “H” shaped emitter has two recesses respectively on two opposite sides of the cross-bar between the two parallel bars. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, each of which has a base via hole near a center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 6, 2018
    Assignee: Win Semiconductors Corp.
    Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
  • Patent number: 9882002
    Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo
  • Patent number: 9871128
    Abstract: There are disclosed herein various implementations of a bipolar semiconductor device with sub-cathode enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes first and second depletion trenches, each having a depletion electrode. In addition, the bipolar semiconductor device includes a first control trench situated between the first and second depletion trenches, the first control trench extending into the drift region and being adjacent to cathode diffusions. An enhancement region having the first conductivity type is localized in the drift region between the first control trench and one or both of the first and second depletion trenches. In one implementation, the bipolar semiconductor device may be an insulated-gate bipolar transistor (IGBT).
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 16, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Gianluca Camuso, Alice Pei-Shan Hsieh, Chiu Ng, Yi Tang, Rajeev Krishna Vytla, Canhua Li
  • Patent number: 9508669
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 29, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Patent number: 9231106
    Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo
  • Patent number: 9024420
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 5, 2015
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8994147
    Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Khalid Hassan Hussein, Shoji Saito
  • Patent number: 8841750
    Abstract: Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: David L. Harame, Zhong-Xiang He, Qizhi Liu
  • Patent number: 8836150
    Abstract: A semiconductor device disclosed in this description has a semiconductor substrate including an element region in which a semiconductor element is formed, and an upper surface electrode formed on an upper surface of the element region of the semiconductor substrate. The upper surface electrode has a first thickness region and a second thickness region which is thicker than the first thickness region, and a bonding wire is bonded on the second thickness region.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 16, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hiroaki Tanaka
  • Patent number: 8680668
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Patent number: 8587101
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 19, 2013
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 8575746
    Abstract: A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Si-Hoon Lee, Sa-Yoon Kang, Kyoung-Sei Choi
  • Patent number: 8569865
    Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 8541833
    Abstract: A semiconductor component includes a sequence of layers, the sequence of layers including a first insulator layer, a first semiconductor layer disposed on the first insulator layer, a second insulator layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the second insulator layer. The semiconductor component also includes a plurality of devices at least partly formed in the first semiconductor layer. A first one of the plurality of devices is a power transistor formed in a first region of the first semiconductor layer and a first region of the second semiconductor layer. The first region of the first and second semiconductor layers are in electrical contact with one another through a first opening in the second insulator layer.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: September 24, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Helmut Strack, Franz Hirler
  • Patent number: 8536680
    Abstract: An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yukio Takahashi, Kousuke Yoshida
  • Patent number: 8530904
    Abstract: A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Treu, Ralf Siemieniec
  • Patent number: 8399907
    Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 19, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee
  • Patent number: 8384194
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 26, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8358014
    Abstract: A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240).
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: January 22, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K Koduri
  • Patent number: 8350371
    Abstract: The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made of Ag for improving heat conductivity between the semiconductor chip and the solid plate.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
  • Patent number: 8330252
    Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Reimund Engl, Thomas Behrens, Wolfgang Kuebler, Rainald Sander
  • Patent number: 8309395
    Abstract: The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer 4? an anti-oxidation layer is applied to the top chip metallization at least in the region of the predefined bond area.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: November 13, 2012
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8299579
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 30, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 8294244
    Abstract: A semiconductor device comprises: a semiconductor substrate; a plurality of IGBT cells on the semiconductor substrate, each of the IGBT cells including a gate electrode and a first emitter electrode; a first gate wiring on the substrate and being connected to the gate electrode; an interlayer insulating film covering the first emitter electrode and the first gate wiring; and a second emitter electrode on the interlayer insulating film and being connected to the first emitter electrode through an opening of the interlayer insulating film, wherein the second emitter electrode extends above the first gate wiring via the interlayer insulating film.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 23, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Yoshifumi Tomomatsu
  • Patent number: 8269304
    Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 18, 2012
    Assignee: Trinno Technology Co., Ltd.
    Inventors: Kwang-Hoon Oh, Byoung-Ho Choo, Soo-Seong Kim, Chong-Man Yun
  • Patent number: 8269308
    Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn
  • Patent number: 8212292
    Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kia Zuo
  • Patent number: 8193618
    Abstract: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Ruben P. Madrid
  • Patent number: 8164162
    Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: April 24, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8124449
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Patent number: 8115280
    Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Shuo-Mao Chen, Chin-Wei Kuo, Sally Liu
  • Patent number: 8076755
    Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: December 13, 2011
    Inventors: Mitsuo Umemoto, Shigehito Matsumoto, Hirotoshi Kubo, Yukari Shirahata, Masamichi Yamamuro, Koujiro Kameyama
  • Patent number: 8008746
    Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 30, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunari Hatade
  • Patent number: 8004008
    Abstract: The first base electrodes and the first emitter electrodes are all formed like strips, and are alternately arranged in parallel, and the area of the second emitter electrode is expanded to be larger than that of the second base electrode. With this, the number of current paths increases in each of which a current is pulled up almost straight from the emitter region to the second emitter electrode through the first emitter electrodes, thereby preventing the current densities of the entire chip from becoming uneven.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: August 23, 2011
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventor: Kazuya Takahashi
  • Patent number: 7952165
    Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Francois Pagette
  • Patent number: 7936047
    Abstract: A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: May 3, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vincenzo Enea, Cesare Ronsisvalle
  • Patent number: 7911032
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: March 22, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 7880288
    Abstract: A semiconductor module has at least two semiconductor chips (4, 5) with at least one first and one second electrode (12, 13) on their first sides. Each semiconductor chip (4, 5) has a third electrode (14) on its second side (16). A chip arrangement within the semiconductor module (1) is provided such that the electrodes (12, 13) on the first sides of the semiconductor chips (4, 5) are oriented toward a second side of the semiconductor module (1) and the third electrodes (14) on the second sides (16) of the semiconductor chips (4, 5) are oriented toward a first side of the semiconductor module (1). For this purpose, external terminals (19, 20) on the second side of the semiconductor module (1) are directly coupled to the electrodes (12, 13) of the first sides and connecting elements (22) electrically couple the third electrodes (14) to corresponding external terminals (21).
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 7772060
    Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: August 10, 2010
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Reiner Jumpertz, Klaus Schimpf
  • Publication number: 20100155895
    Abstract: A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P+ drain region in the P grade region; a first STI region in the P grade region; a second STI region in the P grade region, wherein the first and second STI region isolate the P+ drain region; a third STI region in the deep N well; a gate electrode overlying an area between the second and third STI regions and covering a portion of the second STI region; a gate dielectric layer between the gate electrode and the P type silicon substrate; a P well formed at one side of the third STI region; and a P+ source region in the P well.
    Type: Application
    Filed: December 19, 2008
    Publication date: June 24, 2010
    Inventor: Min-Hsuan Tsai
  • Patent number: 7723824
    Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V).
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Fernando Guarin, J. Edwin Hostetter, Jr., Stewart E. Rauch, III, Ping-Chuan Wang, Zhijian J. Yang
  • Patent number: 7701038
    Abstract: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: April 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Chih-Ping Chao, Chih-Sheng Chang
  • Patent number: 7675113
    Abstract: A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: March 9, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shunsuke Sakamoto, Eisuke Suekawa, Tetsujiro Tsunoda
  • Publication number: 20100052012
    Abstract: The first base electrodes and the first emitter electrodes are all formed like strips, and are alternately arranged in parallel, and the area of the second emitter electrode is expanded to be larger than that of the second base electrode. With this, the number of current paths increases in each of which a current is pulled up almost straight from the emitter region to the second emitter electrode through the first emitter electrodes, thereby preventing the current densities of the entire chip from becoming uneven.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 4, 2010
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventor: Kazuya TAKAHASHI
  • Patent number: 7655977
    Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 ?m resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 ?m and resistivity in te range of 14 to 18 ohm cm.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: February 2, 2010
    Assignee: International Rectifier Corporation
    Inventors: Chiu Ng, Davide Chiola
  • Publication number: 20090302423
    Abstract: An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 10, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yukio Takahashi, Kousuke Yoshida
  • Patent number: 7615846
    Abstract: An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: November 10, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tatsuo Harada
  • Patent number: 7605446
    Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: October 20, 2009
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Nishad Udugampola, Gehan A. J. Amaratunga