With Non-planar Semiconductor Surface (e.g., Groove, Mesa, Bevel, Etc.) Patents (Class 257/586)
  • Patent number: 10170746
    Abstract: A battery electrode in accordance with various embodiments may include: a substrate including a surface configured to face an ion-carrying electrolyte; and a first diffusivity changing region at a first portion of the surface, wherein the first diffusivity changing region is configured to change diffusion of ions carried by the electrolyte into the substrate, and wherein a second portion of the surface is free from the first diffusivity changing region.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: January 1, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Magdalena Forster, Michael Sorger, Katharina Schmut, Bernhard Goller, Philemon Schweizer, Michael Sternad, Thomas Walter
  • Patent number: 10121860
    Abstract: A fin-type bipolar semiconductor device includes a base region having a first portion in a semiconductor substrate and a first semiconductor fin on the adjacent first portion, a collector region having a second portion in the semiconductor substrate and a second semiconductor fin on the adjacent second portion, and an emitter region having a third region in the semiconductor substrate and a third semiconductor fin on the adjacent third portion. The second portion is adjacent the first portion, and the third portion is adjacent the first portion and forms an emitter junction in the semiconductor substrate. The second portion is not adjacent to the third portion. The first, second, and third semiconductor fins are physically separated from each other. The fin-type bipolar device exhibits low leakage current, good linearity and uniformity of electrical characteristics to facilitate device matching.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 6, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10002954
    Abstract: Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Patent number: 9905668
    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Patent number: 9850569
    Abstract: A method of forming a superconductor tape, includes depositing a superconductor layer on a substrate, forming a metal layer comprising a first metal on a surface of the superconductor layer, and implanting an alloy species into the metal layer where the first metal forms a metal alloy after the implanting the alloy species.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: December 26, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Ludovic Godet, Frank Sinclair, Morgan Evans
  • Patent number: 9653305
    Abstract: A semiconductor component includes semiconductor fins formed between a base plane and a main surface of a semiconductor body. Each semiconductor fin includes a source region formed between the main surface and a channel/body region, and a drift zone formed between the channel/body region and the base plane. The semiconductor component further includes gate electrode structures on two mutually opposite sides of each channel/body region, and a field electrode structure between mutually adjacent ones of the semiconductor fins. Each field electrode structure is separated from the drift zone by a field dielectric and extends from the main surface as far as the base plane. The gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from two sides.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Stefan Tegen, Marko Lemke, Rolf Weis
  • Patent number: 9245951
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 9006833
    Abstract: A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Akram A. Salman
  • Patent number: 8981444
    Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 17, 2015
    Assignee: Round Rock Research, LLC
    Inventors: Kevin J. Torek, Mark Fischer, Robert J. Hanson
  • Publication number: 20150060950
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.
    Type: Application
    Filed: October 29, 2014
    Publication date: March 5, 2015
    Inventors: Renata Camillo-Castillo, Marwan H. Khater
  • Patent number: 8946862
    Abstract: Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8933536
    Abstract: Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: January 13, 2015
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Chung H. Lam, Bipin Rajendran
  • Patent number: 8933537
    Abstract: A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein t
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: January 13, 2015
    Assignee: IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut fur Innovative Mikroelekronik
    Inventors: Alexander Fox, Bernd Heinemann, Steffen Marschmeyer
  • Patent number: 8932911
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Torsten Huisinga, Carsten Peters, Andreas Ott, Axel Preusse
  • Publication number: 20150008562
    Abstract: Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: David L. Harame, Qizhi Liu
  • Patent number: 8912529
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8912094
    Abstract: Provided is a method for manufacturing a stretchable thin film transistor. The method for manufacturing a stretchable thin film transistor includes forming a mold substrate, forming a stretchable insulator on the mold substrate, forming a flat substrate on the stretchable insulator, removing the mold substrate, forming discontinuous and corrugated wires on the stretchable insulator, forming a thin film transistor connected between the wires, and removing the flat substrate.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 16, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Bon Koo, Chan Woo Park, Soon-Won Jung, Sang Chul Lim, Ji-Young Oh, Bock Soon Na, Hye Yong Chu
  • Patent number: 8912631
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 16, 2014
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Patent number: 8901713
    Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140339677
    Abstract: A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction. An insulator layer is upon one side the base layer and emitter region. Base and emitter electrodes are isolated from each other by the insulator layer and electrically contact the base layer and emitter region through the insulator layer. A thin and flexible collector layer is upon an opposite side of the base layer. A microcavity is formed in the collector layer and is aligned with the emitter region. Collector electrodes are arranged to sustain a microplasma within the microcavity with application of voltage to the collector electrodes. A depth of the emitter region and a thickness of the base layer are set to define a predetermined thin portion of the base layer as a base region between the emitter region and the microcavity. Microplasma generated in the microcavity serves as a collector.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Inventors: J. Gary Eden, Paul A. Tchertchian, Clark J. Wagner, Dane J. Sievers, Thomas J. Houlahan, Benben Li
  • Publication number: 20140327111
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Marwan H. Khater
  • Publication number: 20140319654
    Abstract: Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). A preferred device is a hybrid plasma semiconductor device having base, emitting and microcavity collector regions formed on a single side of a device layer. Visible or ultraviolet light is emitted during operation by plasma collectors in the array. In preferred embodiments, individual PBJTs in the array serve as sub-pixels of a full-color display.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventors: J. Gary Eden, Paul A. Tchertchian, Clark J. Wagner, Dane J. Sievers, Thomas J. Houlahan, Benben Li
  • Patent number: 8853826
    Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Yao Lai, Shyh-Wei Wang, Yen-Ming Chen
  • Patent number: 8847359
    Abstract: High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Gerard Balster, Hiroshi Yasuda, Philipp Steinmann, Badih El-Kareh
  • Patent number: 8847278
    Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Manabu Takei, Yusuke Kobayashi
  • Patent number: 8729675
    Abstract: A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jay-Bok Choi, Kyu-Hyun Lee, Mi-Jeong Jang, Young-Jin Choi, Ju-Young Huh
  • Patent number: 8716837
    Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Peter B. Gray, David L. Harame, Alvin J. Joseph, Marwan H. Khater, Qizhi Liu
  • Patent number: 8716836
    Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: May 6, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masahiko Hata, Taketsugu Yamamoto, Kazumi Wada
  • Publication number: 20140111892
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8669640
    Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8637959
    Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: January 28, 2014
    Assignee: Shanghai Hua Hong NEC Electronics
    Inventors: Wensheng Qian, Donghua Liu, Jun Hu
  • Publication number: 20130299944
    Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Yao Lai, Shyh-Wei Wang, Yen-Ming Chen
  • Publication number: 20130285120
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×1016 cm?3. According to certain embodiments, the collector includes two gradings. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Skyworks Solutions, Inc.
    Inventor: Peter J. Zampardi, JR.
  • Publication number: 20130277804
    Abstract: Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Cheng, David L. Harame, Robert K. Leidy, Qizhi Liu
  • Patent number: 8536012
    Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Peter B. Gray, David L. Harame, Alvin J. Joseph, Marwan H. Khater, Qizhi Liu
  • Patent number: 8525187
    Abstract: An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: September 3, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Keiji Wada, Toru Hiyoshi
  • Patent number: 8525301
    Abstract: A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: September 3, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Tahir Hussain
  • Patent number: 8502236
    Abstract: A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Keiji Wada, Toru Hiyoshi
  • Patent number: 8502347
    Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: August 6, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8497552
    Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 30, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8466045
    Abstract: A method for forming strained epitaxial carbon-doped silicon (Si) films, for example as raised source and drain regions for electronic devices. The method includes providing a structure having an epitaxial Si surface and a patterned film, non-selectively depositing a carbon-doped Si film onto the structure, the carbon-doped Si film containing an epitaxial carbon-doped Si film deposited onto the epitaxial Si surface and a non-epitaxial carbon-doped Si film deposited onto the patterned film, and non-selectively depositing a Si film on the carbon-doped Si film, the Si film containing an epitaxial Si film deposited onto the epitaxial carbon-doped Si film and a non-epitaxial Si film deposited onto the non-epitaxial carbon-doped Si film. The method further includes dry etching away the non-epitaxial Si film, the non-epitaxial carbon-doped Si film, and less than the entire epitaxial Si film to form a strained epitaxial carbon-doped Si film on the epitaxial Si surface.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: June 18, 2013
    Assignee: Tokyo Electron Limited
    Inventors: John Gumpher, Seungho Oh, Anthony Dip
  • Publication number: 20130146894
    Abstract: The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: CREE, INC.
    Inventors: Lin Cheng, Anant K. Agarwal, Sei-Hyung Ryu
  • Publication number: 20130147017
    Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Publication number: 20130134483
    Abstract: Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: International Business Machines Corporation
    Inventors: James W. Adkisson, John J. Ellis-Monaghan, David L. Harame, Qizhi Liu, John J. Pekarik
  • Publication number: 20130092939
    Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.
    Type: Application
    Filed: July 6, 2012
    Publication date: April 18, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Nam Joo KIM
  • Patent number: 8384194
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 26, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8378390
    Abstract: The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts (1, 2) on the transistor is given a negative electric surface potential with respect to the potential in the bulk SiC. The present disclosure also relates to a method for increasing the current gain in a silicon carbide (SiC) bipolar junction transistor (BJT) by the reduction of the surface recombination at the SiC surface between the emitter and base contacts (1, 2) of the transistor.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 19, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Martin Domeij
  • Patent number: 8368181
    Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: February 5, 2013
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
  • Patent number: 8362595
    Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 29, 2013
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
  • Patent number: 8357972
    Abstract: A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: January 22, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Yi-Chun Shih