Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.

Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.

Abstract: The embodiments described herein generally relate to methods for forming a multi-layer amorphous silicon structure that may be used in thin film transistor devices. In one embodiment, a method includes positioning a substrate comprising a buffer layer in a process chamber, the process chamber comprising a processing region, forming a plurality of amorphous silicon layers and annealing the amorphous silicon layers to form a polycrystalline silicon layer. Forming the plurality of layers includes delivering a silicon-containing precursor and a first activation gas to the processing region to deposit a first amorphous silicon layer over the buffer layer, the silicon-containing precursor and the first activation gas being activated by a plasma and maintaining a continuous flow of the silicon-containing precursor while delivering a second activation gas, without the first activation gas, to the processing region to deposit a second silicon layer on the first silicon layer.

Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.

Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

Abstract: A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3.

Abstract: Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

Abstract: Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.

Abstract: In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.

Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

Abstract: In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.

Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.

Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and t

Abstract: A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

Abstract: According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating layer situated on the base oxide layer. The bipolar transistor further includes an emitter situated over the top surface of the base and the antireflective coating layer, where a layer of polysilicon is not situated between the base oxide layer and the emitter.

Abstract: Methods and apparatuses directed to low base resistance bipolar junction transistor (BJT) devices are described herein. A low base resistance BJT device may include a collector layer, a base layer formed on the collector layer, a plurality of isolation trench lines formed in the base layer and extending into the collector layer, and a plurality of polysilicon lines formed on the base layer parallel to and overlapping the plurality of isolation trench lines. The base layer may be N-doped or P-doped.

Abstract: A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively.

Abstract: A thin film electron source comprising a substrate, a lower electrode formed on one main face of said substrate, an insulation layer formed in contact with said lower electrode and an upper electrode formed in contact with said insulation layer. The upper electrode comprises a first under-layer, a second under-layer, an intermediate layer and a surface layer laminated from the insulation layer side. A main material of the first under-layer is IrO2 or RuO2; a main material of the second under-layer is Ir or Ru, and a main material of the surface layer is a member selected from the group consisting of Au and Ag.

Abstract: Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.

Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

Abstract: A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

Abstract: A bipolar transistor includes an isolation layer formed in a bipolar region on a semiconductor substrate, a conductive film formed over an upper portion of the isolation layer, n+ and p+ junction regions formed within the conductive film, a first silicide film formed over portions of an upper boundary of the n+ and p+ junction regions, the first silicide film defining openings over the upper boundary of the n+ and p+ junction regions, a second silicide film formed in the openings defined by the first silicide film over the upper boundary portions of the n+ and p+ junction regions, a plurality of plugs connected to the second silicide film, and a plurality of electrodes connected to each of the plugs.

Abstract: A method for forming a self-aligned bipolar transistor structure uses the selective growth of a doped silicon emitter in a sloped oxide emitter window to form the self-aligned structure. In an alternate process flow, the top emitter layer is SiGe with a high Ge content that is etched off selectively after deposition of the extrinsic base layer. In another alternate flow, a nitride plug formed on top of the emitter blocks the extrinsic base implant from the emitter region.

Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

Abstract: A transistor assembly having a transistor includes a plurality of transistor regions, each of which has a vertical transistor structure having a collector semiconductor region, a base semiconductor region and an emitter semiconductor region, emitter contacting regions arranged above the transistor regions and base contacting regions connected to the base semiconductor regions via a polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer is structured such that the base contacting regions of transistor regions which are not part of the transistor are electrically isolated from base contacting regions of transistor regions which are part of the transistor.

Abstract: In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region for a collector electrode are brought into direct contact with each other to prevent formation of an unnecessary isolation region. Further, an emitter region is disposed to self-align with a device isolation insulating film or a polycrystalline silicon arranged on a surface of a semiconductor substrate.

Abstract: A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper peripheral region of the base region, an emitter region in contact with the central portion of the base region. The level of the central portion is higher than the level of the intermediary portion.

Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) comprising a first, a second and a third connection conductor, which emitter region (1) comprises a mesa-shaped emitter connection region (1A) provided with spacers (4) and adjacent thereto a base connection region (2A) comprising a conductive region (2AA) of poly crystalline silicon. In a device (10) according to the invention, the base connection region (2A) comprises a further conducting region (2AB), which is positioned between the conductive region (2AA) of poly crystalline silicon and the base region (2) and which is made of a material with respect to which the conducting region (2AA) of polycrystalline silicon is selectively etchable. Such a device (10) is easy to manufacture by means of a method according to the invention and its bipolar transistor possesses excellent RF properties.

Abstract: Disclosed are a bipolar transistor comprising an emitter terminal and a base terminal having substantially equal heights, and a method of fabricating the same. The bipolar transistor comprises a silicon-germanium layer acting as a base and formed on a semiconductor layer acting as a collector. The bipolar transistor further comprises an insulating layer having contact windows for an emitter terminal and a collector terminal. The emitter and collector terminals are formed by forming a polysilicon layer filling the contact windows and performing a planarization process on the polysilicon layer. An ion implantation process is performed to form a polysilicon emitter terminal and a polysilicon base terminal.

Abstract: The present invention provides a technology that makes it possible to enhance the gain and the efficiency of an RF bipolar transistor. Device isolation is given between a p+ type isolation region and an n+ type collector embedded region and between a p+ type isolation region and an n type collector region (an n+ type collector extraction region) with an isolation section that surrounds the collector extraction region in a plan view and is formed by embedding a dielectric film in a groove penetrating an isolation section, a collector region, and a collector embedded region and reaching a substrate. Further, a current route is formed between an emitter wiring (a wiring) and the substrate with an electrically conductive layer formed by embedding the electrically conductive layer in a groove penetrating a dielectric film, silicon oxide films, a semiconductor region, and the isolation regions and reaching the substrate, and thereby the impedance between the emitter wiring and the substrate is reduced.

Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Abstract: A bipolar transistor and a method for manufacturing the same. The bipolar transistor can include a collector region formed in a substrate, an epitaxial layer formed over the substrate including the collector region, a base region formed in the epitaxial layer, an emitter region formed in the base region, an oxide layer formed on sidewalls of a trench extending through the emitter region, the base region, the epitaxial layer and in the collector region, and a polysilicon layer formed in the trench.

Abstract: Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.

Abstract: A bipolar junction transistor includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a semiconductor layer formed on a sidewall and a bottom of the opening and on a portion of the dielectric layer outside the opening, a spacer formed on the semiconductor layer to define a self-aligned emitter region in the opening, an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the semiconductor layer, and a salicide layer formed on the emitter conductivity layer and on the portion of the semiconductor layer extending outside the opening.

Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.

Abstract: The present invention is related to a semiconductor device that forms an inductor on the same semiconductor substrate together with other active elements and a manufacturing method thereof. The semiconductor device of the present invention comprises a first conductivity type substrate, first semiconductor layer of a first conducting type with an impurity concentration lower than the substrate and a second semiconductor layer of a second conducting type on the first layer, an insulating film formed on this high-resistance semiconductor layer, and an inductor formed on this insulating film. The inductor has conducting film defining a width of the inductor. The first and second semiconductor layers are each formed under and at least as long as the width of the inductor.

Abstract: A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface layer; a base contact (130 and 131) extending through a substantial portion (141) of the surface layer, spaced apart (140a) from the emitter; an insulator region (150/151) buried under the base contact; a collector contact (120); and a first polycrystalline semiconductor region (152/153) selectively located under the insulator region, and a second polycrystalline semiconductor region (154) selectively located under the collector contact. These polycrystalline regions exhibit heavy dopant concentrations of the first conductivity type; consequently, they lower the collector resistance.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: An aspect of a semiconductor device includes: a collector layer of first conductive type formed on a semiconductor substrate; a graft base layer of second conductive type formed in a surface region of the collector layer; a first base leading-out region of second conductive type formed on the graft base layer; a second base leading-out region of second conductive type formed on an upper surface and a side surface of the first base leading-out region; a base layer of second conductive type formed on the collector layer; an emitter layer of first conductive type formed in a surface region of the base layer; and an emitter leading-out region formed on the emitter layer.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portions of the doped area. A P-type epitaxy layer is formed on the protection layer and the first doped area and then portions of the epitaxy layer and the protection layer are removed. An insulation layer is formed and at least a collector opening and emitter opening are formed within the insulation layer. Following that, a polysilicon layer is formed to fill the collector opening and the emitter opening. A spacer is formed beside the polysilicon layer and the epitaxy layer followed by performing a self-aligned silicidation process to form a salicide layer on the polysilicon layer and portions of the epitaxy layer.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.

Abstract: A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked on the CVD ultra-thin titanium nitride film, a tungsten layer stacked on the tungsten nitride layer, and a nitride cap layer stacked on the tungsten layer. A liquid phase deposition (LPD) oxide spacer is formed on each sidewall of the metal gate stack. A silicon nitride spacer is formed on the LPD oxide spacer. The thickness of the CVD ultra-thin titanium nitride film is between 10 and 100 angstroms.

Abstract: The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first doped region flanked by a set of second doped regions; a phase change material positioned on the first doped region; and a conductor positioned on the phase change material, wherein when the phase change material is a first phase the semiconductor structure operates as a bipolar junction transistor, and when the phase change material is a second phase the semiconductor structure operates as a field effect transistor.

Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.