With Specified Electrode Means Patents (Class 257/587)
  • Patent number: 10777524
    Abstract: A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, Michael Meeder
  • Patent number: 9917048
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 9761685
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshikazu Hanawa
  • Patent number: 9673309
    Abstract: A p-layer on a surface layer of one of n? drift layers is separated into a p-base-region and a floating p-region by a plurality of trenches. A first gate electrode is disposed on a side wall of the trench on the p-base-region side via a first insulation film, and a shield electrode is disposed on a side wall of the trench on the floating p-region side via a second insulation film. Between the first gate electrode conductively connected to a gate runner via a contact plug embedded in a first contact hole and the shield electrode conductively connected to an emitter electrode via a contact plug embedded in a second contact hole, an insulation film reaches from the front surface of the substrate to the bottom surface of the trench. Hence, the fabrication process can be shortened to provide a highly reliable semiconductor device with low switching loss.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 6, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 9666666
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: May 30, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Patent number: 9576942
    Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 9553177
    Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
  • Patent number: 9490352
    Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 8, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 9419193
    Abstract: An opto-electronic component has a carrier element (3) with a connection region (5). Arranged on the carrier element (3) is a semiconductor chip (7). A contact region (10) is mounted on the surface (8) of the semiconductor chip (7) remote from the carrier element (3). The connection region (5) is electrically conductively connected to the contact region (10) by way of an unsupported conductive structure (13). A method for manufacturing an opto-electronic component is described.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: August 16, 2016
    Assignees: OSRAM Opto Semiconductors GmbH, Siemens Aktiengesellschaft
    Inventors: Bernd Barchmann, Axel Kaltenbacher, Norbert Stath, Walter Wegleiter, Karl Weidner, Ralph Wirth
  • Patent number: 9209109
    Abstract: An IGBT includes a semiconductor portion with IGBT cells. Each IGBT cell includes a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, and a drift zone of the first conductivity type separated from the source zone by the body zone. An emitter electrode includes a main layer and an interface layer. The interface layer directly adjoins at least one of the body zone and a supplementary zone of the second conductivity type. A contact resistance between the semiconductor portion and the interface layer is higher than between the semiconductor portion and a material of the main layer. For example, the interface layer may reduce diode emitter efficiency and reverse recovery losses in IGBTs.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Thomas Gutt, Mathias Plappert, Frank Pfirsch
  • Patent number: 9202704
    Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: December 1, 2015
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Miguel Urteaga, Richard L. Pierson, Jr., Keisuke Shinohara
  • Patent number: 9194884
    Abstract: An integrated circuit with analog device fault detection includes an integrated circuit die having an analog device, an on-line fault detector and a control circuit. The analog device has a power input, an analog device input and an analog device output and the on-line fault detector is coupled to at least one of the power input, the analog device input and the analog device output and has a fault detector output. The control circuit is coupled to the fault detector and responsive to the fault detector output. Detector self-test (DST) circuitry can be provided to test the on-line fault detector and one or more circuit breakers can be provided to protect the analog device and other devices attached to the analog device.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: November 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: John Archie Mossman, Robert A. McCarthy
  • Patent number: 9166018
    Abstract: When forming a p+ area and n+ area on the same surface of an n? semiconductor wafer, a first ion implantation forms the p+ area on the entire rear surface of the n? semiconductor wafer. Next, a resist mask selectively covering the rear surface of the n? semiconductor wafer is formed. With this resist mask as the mask, an n-type impurity is injected into the rear surface of the n? semiconductor wafer through a second ion implantation to form the n+ area on a portion deeper from the rear surface of the n? semiconductor wafer than the p+ type area. Thereafter, the n? semiconductor wafer is exposed to an oxygen (O2) gas atmosphere with fluorine (F) gas added to remove the resist mask and a silicon part between the rear surface of the n? semiconductor wafer in an FWD area not covered by the resist mask and the n+ area.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 20, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshihito Kamei, Seiji Noguchi
  • Patent number: 9105678
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 11, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Publication number: 20150130025
    Abstract: The invention provides a method for fabricating a transistor and a transistor, wherein the method for fabricating a transistor includes: growing a second oxide layer on the surface of a substrate on which a first oxide layer and a first base region are formed, wherein the second oxide layer is formed above the first base region; forming an emitter region in a first preset area on the second oxide layer; forming a contact hole in a second preset area on the second oxide layer, wherein the second preset area does not overlap with the first preset area; injecting doping elements into the surface of the first base region in the area of the contact hole; and thermally processing the substrate to activate the doping elements to form a second base region.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 14, 2015
    Inventors: Guangran PAN, Yan WEN, Kun WANG
  • Patent number: 9013000
    Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first metal gate electrode provided in a NMOS region of a substrate; and a second metal gate electrode provided in a PMOS region of the substrate, wherein the first and second metal gate electrodes may be formed of TiN material or TiAlN material. Here, the first metal gate electrode may have a higher titanium (Ti) content than the second metal gate electrode, and the second metal gate electrode may have a higher nitrogen (N) content than the first metal gate electrode.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignees: SK Hynix Inc., Industry-University Cooperation Foundation Hanyang University
    Inventor: Chang-Hwan Choi
  • Patent number: 8933537
    Abstract: A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein t
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: January 13, 2015
    Assignee: IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut fur Innovative Mikroelekronik
    Inventors: Alexander Fox, Bernd Heinemann, Steffen Marschmeyer
  • Patent number: 8933536
    Abstract: Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: January 13, 2015
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Chung H. Lam, Bipin Rajendran
  • Patent number: 8912632
    Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 8907454
    Abstract: A transistor includes: a semiconductor substrate; a first electrode on the semiconductor substrate and having first and second portions; a second electrode on the semiconductor substrate and spaced apart from the first electrode; a control electrode on the semiconductor substrate and disposed between the first electrode and the second electrode; and a first heat sink plate joined to the second portion of the first electrode without being joined to the first portion of the first electrode.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinobu Sasaki, Hitoshi Kurusu
  • Patent number: 8866264
    Abstract: A semiconductor device implemented with structures to suppress leakage current generation during operation and a method of making the same is provided. The semiconductor device includes a semiconductor substrate of first conductivity type, a second insulation film, which has at least one aperture between first and second apertures, formed on top of a first insulation film. The semiconductor device layer structure accommodates tensile stress differences between device layers to suppress lattice dislocation defects during device manufacturing and thus improves device reliability and performance.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kubo
  • Patent number: 8860092
    Abstract: A heterojunction bipolar transistor having an emitter, a base, and a collector, the heterojunction bipolar transistor including a metallic sub-collector electrically and thermally coupled to the collector wherein the metallic sub-collector comprises a metallic thin film, and a collector contact electrically connected to the metallic sub-collector.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: October 14, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Donald A. Hitko, Yakov Royter, Pamela R. Patterson
  • Patent number: 8853827
    Abstract: In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 7, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Martin Domeij
  • Patent number: 8841750
    Abstract: Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: David L. Harame, Zhong-Xiang He, Qizhi Liu
  • Patent number: 8735955
    Abstract: A grounding system for a semiconductor module of a variable speed drive includes a first conductive layer, a second conductive layer; a substrate disposed between the first conductive layer and the second conductive layer; and a base attached to the second conductive layer, the base being connected to earth ground via a grounding harness. The first conductive layer is in electrical contact with the semiconductor module and the substrate, and electrically insulated from the second conductive layer by the substrate. The second conductive layer is in electrical contact with the substrate and disposed between the substrate and the base in electrical communication with an earth ground. The first conductive layer, the substrate and the second conductive layer form a capacitance path between the semiconductor module and the base as well as electrical conductors and the base for reduction circulating currents within the semiconductor module.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 27, 2014
    Assignee: Johnson Controls Technology Company
    Inventors: Konstantin Borisov, Michael S. Todd, Shreesha Adiga-Manoor, Ivan Jadric
  • Publication number: 20140104013
    Abstract: An apparatus, system, and method are disclosed for modulating electric current. An electron source electrode 202 provides a flow of electrons in a partial vacuum environment 116. An ionizable gas 118 in the partial vacuum environment 116 forms positively charged ion particles in response to impact with the electrons from the electron source electrode 202. Application of a bias voltage differential between a first bias electrode 204 and a second bias electrode 206 in the partial vacuum environment 116 forms an electric field gradient in a path of the flow of electrons. A collector electrode 208 in the partial vacuum environment 116 collects more electrons than ion particles when a collector electrode input voltage 106 is above a threshold, and collects more ion particles than electrons when the collector electrode input voltage 106 is below the threshold.
    Type: Application
    Filed: June 21, 2012
    Publication date: April 17, 2014
    Applicant: RESEARCH TRIANGLE INSTITUTE, INTERNATIONAL
    Inventors: Brian Stoner, Jeffrey Piascik
  • Patent number: 8679969
    Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 25, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Miguel Urteaga, Richard L. Pierson, Jr., Keisuke Shinohara
  • Patent number: 8664692
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino
  • Patent number: 8575768
    Abstract: A radiation-curable ink jet ink composition contains a polymerizable compound, an photopolymerization initiator and polysiloxane, in which the ink composition is used for recording on a package substrate as a recording medium; the polymerizable compound contains one or more kinds of compound having a pentaerythritol skeleton; an HLB value of the polysiloxane is 5 to 12; and the polysiloxane content is 0.1 to 2% by mass with respect to the total amount of the ink composition.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: November 5, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Hiroki Nakane, Jun Ito
  • Patent number: 8564142
    Abstract: The invention provides a radiation curable ink jet ink composition including: a monomer equal to or more than 20% by mass and equal to or less than 50% by mass with respect to the total mass of the ink composition, which is represented by the following formula (I); and N-vinylcaprolactam equal to or more than 5% by mass and equal to or less than 15% by mass with respect to the total mass of the ink composition: CH2?CR1—COOR2—O—CH?CH—R3??(I) wherein, R1 is a hydrogen atom or a methyl group, R2 is a divalent organic residue having 2 to 20 carbon atoms, and R3 is a hydrogen atom or monovalent organic residue having 1 to 11 carbon atoms.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Jun Ito, Hiroki Nakane
  • Publication number: 20130221401
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.
    Type: Application
    Filed: August 30, 2012
    Publication date: August 29, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuichi OSHINO
  • Patent number: 8497527
    Abstract: A device comprising a two-dimensional electron gas that includes an active region located in a portion of the electron gas is disclosed. The active region comprises an electron concentration less than an electron concentration of a set of non-active regions of the electron gas. The device includes a controlling terminal located on a first side of the active region. The device can comprise, for example, a field effect transistor (FET) in which the gate is located and used to control the carrier injection into the active region and define the boundary condition for the electric field distribution within the active region. The device can be used to generate, amplify, filter, and/or detect electromagnetic radiation of radio frequency (RF) and/or terahertz (THz) frequencies.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: July 30, 2013
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexei Koudymov, Michael Shur, Remigijus Gaska
  • Publication number: 20130153028
    Abstract: A thin-film transistor according to the present disclosure is capable of balancing excellent on-characteristics and excellent off-characteristics, and in which the electrical characteristics are symmetric even when the source electrode and the drain electrode are switched. The thin-film transistor includes: a substrate; a gate electrode; a gate insulating layer; a crystalline silicon layer above the gate insulating layer above the gate electrode; a non-crystalline silicon layer above the gate insulating layer and on both sides of the crystalline silicon layer, having a thickness smaller than a thickness of the crystalline silicon layer; a channel protective layer above the crystalline silicon layer; and a source electrode and a drain electrode.
    Type: Application
    Filed: February 21, 2013
    Publication date: June 20, 2013
    Applicants: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC CORPORATION
    Inventors: PANASONIC CORPORATION, PANASONIC LIQUID CRYTAL DISPLAY CO., LTD.
  • Patent number: 8455306
    Abstract: Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: June 4, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amaury Gendron, Chai Ean Gill, Rouying Zhan
  • Patent number: 8410572
    Abstract: A base contact connection, an emitter structure and a collector structure are arranged on an n-layer, which can be provided for additional npn transistors. The collector structure is arranged laterally to the emitter structure and at least one of the emitter and collector comprises a Schottky contact on a surface area of the n-layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 2, 2013
    Assignee: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Patent number: 8384193
    Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8378457
    Abstract: A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 19, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Wensheng Qian, Zhengliang Zhou
  • Publication number: 20130037914
    Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 14, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
  • Publication number: 20130032927
    Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Inventors: Miguel Urteaga, Richard L. Pierson, JR., Keisuke Shinohara
  • Patent number: 8319315
    Abstract: A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: November 27, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Cheng-Chi Lin, Wei-Hsun Hsu, Shuo-Lun Tu, Shih-Chin Lien, Chin-Pen Yeh
  • Publication number: 20120261799
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
  • Patent number: 8269313
    Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Akio Matsuoka
  • Publication number: 20120223336
    Abstract: A semiconductor device includes a semiconductor substrate including a collector layer of a first conductivity type and a drift layer of a second conductivity type in contact with said collector layer, said drift layer receiving a supply of carriers from said collector layer. The semiconductor device further includes a lattice defect formed to penetrate through said semiconductor substrate and enclose a predetermined portion of said semiconductor substrate, a sense emitter electrode formed on the top surface of said predetermined portion, and a collector electrode formed on the bottom surface of said predetermined portion.
    Type: Application
    Filed: November 22, 2011
    Publication date: September 6, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Shunsuke SAKAMOTO
  • Publication number: 20120187538
    Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 26, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8188568
    Abstract: A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer formed in the upper part of the first diffusion layer; and a fifth diffusion formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. The substrate, the second and the fifth diffusion layer are a first conductivity type and the others are a second conductivity type.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: May 29, 2012
    Assignee: Panasonic Corporation
    Inventor: Manabu Imahashi
  • Publication number: 20120119331
    Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
  • Publication number: 20120104555
    Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.
    Type: Application
    Filed: October 31, 2010
    Publication date: May 3, 2012
    Inventors: Madhur Bobde, Anup Bhalla
  • Patent number: 8159048
    Abstract: Embodiments of methods, apparatus, devices and/or systems associated with bipolar junction transistor are disclosed.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 17, 2012
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Thomas R. Apel, Jeremy R. Middleton
  • Patent number: 8129819
    Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: March 6, 2012
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8124449
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl