Abstract: A semiconductor device comprises a semiconductor substrate having a main surface, a first semiconductor region of a first conductive type, formed on the main surface of the semiconductor substrate, a surrounding of the first semiconductor region is buried with a first insulation film, a second semiconductor region of a second conductive type, formed on the first insulation film and the first semiconductor region, a second insulation film, formed on the second semiconductor region, an end portion of the second insulation film is positioned above the first insulation film, and having an opening at a central portion thereof to be positioned above the first semiconductor region, and a third semiconductor region of a first conductivity type formed on a surface of the second semiconductor region exposed through the opening of the second insulation film.

Abstract: A low-noise NPN transistor comprising a cut-off region laterally surrounding, at a given distance, the emitter region in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. The cut-off region is formed by a P ring astride a P.sup.- type well region and the epitaxial layer.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118).A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to fore an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: In a semiconductor device which includes a semiconductor substrate, a collector region of a first conductivity type formed on the semiconductor substrate, a base region of a second conductivity type reverse to the first conductivity type, an emitter region of the first conductivity type formed within the base region, an intermediate semiconductor layer of the second conductivity type is formed within the collector region, an additional semiconductor layer of the first conductivity type is superposed on the intermediate semiconductor layer, and the base region is overlaid on the additional semiconductor layer.

Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semi-conducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

Abstract: A collector-up bipolar transistor having an undercut region (522) beneath extrinsic regions of a base layer (510) and an emitter layer (508). The extrinsic emitter region is depleted of charge carriers and provides passivation for the extrinsic portion of the base layer (508). Contact to the emitter layer may be made by forming contacts on the top surface of the substrate (500) or in a recess in the backside of the substrate.

Abstract: A bipolar transistor has a base rink structure epitaxially grown from an overhang portion of a poly-crystal silicon base electrode and an epitaxial collector layer and an intrinsic base structure grown on a concave central portion of the base rink structure after a diffusion stage of a dopant impurity into the base rink structure, and the intrinsic base structure is electrically connected through a buried collector region passing through the concave central portion into an epitaxial collector layer, thereby maintaining the dopant impurity profile in the intrinsic base structure without deterioration of transistor characteristics.

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.

Abstract: A bipolar transistor with a structure such that it is possible to reduce the parasitic capacity without sacrificing improvements in cut-off frequency f.sub.T, in which a P.sup.+ -type polycrystalline silicon film 122A is provided on the side wall of an opening 143A which is provided in a silicon nitride film 152A serving as the middle layer of a laminated insulation film 107A, and, a P-type single crystal silicon layer 121A constituting the intrinsic base region is connected to a P.sup.+ -type polycrystalline silicon film 111 which is a base drawing electrode via a thin P.sup.+ -type polycrystalline silicon film 123A.

Abstract: The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract: There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

Abstract: A bipolar lateral transistor, for example of the pnp type, is contained in a semiconductor device. The lateral transistor has a p-type emitter region and a p-type collector region laterally spaced apart by an n-type base region. This lateral transistor is formed in an n-type epitaxial layer at the surface of a p-type substrate. The transistor further has a n.sup.++ -type buried layer. The current gain in this lateral transistor is strongly increased by forming the emitter from a first partial emitter region which is weakly p-type doped and extends below an insulating layer, and a second partial emitter region which is strongly P.sup.++ -type doped and extends below the contact zone of the emitter, which is defined by an opening in the insulating layer. The respective thicknesses and doping levels of the first and second emitter regions are provided such that the first region is transparent to electrons and the second region forms a screen against electrons.

Abstract: An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjacent stripes are shifted or offset relative to each other. This causes the emitter pieces which are added to connect adjacent emitter stripes to be staggered with respect to each other. As a result, all sections of the emitters face a base contact and the resistance encountered along a current path between a base contact and an emitter is reduced. This results in a vertical bipolar transistor having a larger proportion of highly activated emitter, better high-frequency performance, and a reduction in thermal noise owing to transistor base resistance.

Abstract: A back gate bias voltage is applied to the underside of a lateral bipolar transistor to desensitize a portion of the collector-base depletion region to changes in the collector-base voltage. Emitter-collector current flows through an active base region bypassing the portion of the collector-base depletion region that remains sensitive to the collector bias. This allows for a control over the charge in the active base region by the back gate bias, generally independent of the collector-base bias. The transistor is preferably implemented in a silicon-on-insulator-on-silicon (SOIS) configuration, with the back gate bias applied to a doped silicon substrate. The base doping concentration and the thickness of the underlying insulator are preferably selected to produce an inversion layer in the base region adjacent the insulating layer, thereby reducing the collector access resistance.

Abstract: The invention described herein includes, in one of its forms, a method for fabricating a bipolar transistor having a reduced base-collector capacitance. A specific embodiment includes forming a selectively etchable material 44 over a highly doped subcollector layer 42, removing portions of the selectively etchable material 44 and then growing collector 46, base 48, and emitter 50 layers over the structure. The selectively etchable material 44 may then be removed to form an undercut region between the highly doped subcollector layer 42 and the highly doped base 48. The structure provides the advantage of improved high-frequency and high-power operation.

Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Abstract: A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract: A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract: A semiconductor device consisting of epitaxial material is provided with at least one monoatomic layer of doping atoms, i.e. with a layer which is just one atom thick. A preferred device is a bipolar transistor in which case the Dirac-delta doped p-type layer 38 is directly between n-type collector and emitter layers (32, 33). The bipolar transistor described herein has an extremely low base width and is capable of operating at high frequencies.

Abstract: A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].

Abstract: A bipolar transistor with a trench. The trench extends down into a buried collector region through an emitter region, the underlying intrinsic base and collector regions at their center portion. Insulating films are formed on the sidewalls of the trench. The trench is filled with a collector-connection conductor which contacts with the buried collector region.

Abstract: A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed laterally about an intrinsic region. An n+ emitter is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract: In a very high speed bipolar transistor, an n.sup.+ -type GaAs collector layer and an n-type GaAs collector layer are stacked in an intrinsic transistor region, and an i-type GaAs collector layer is formed around the n.sup.+ -type GaAs collector layer and the n-type GaAs collector layer. An n-type GaAs collector layer is formed on the n.sup.+ -type GaAs collector layer such that a part of the n-type GaAs collector layer extends on the i-type GaAs collector layer. A p-type GaAs external base layer is formed outside the n-type GaAs collector layer. A p.sup.+ -type Al.sub.x Ga.sub.l-x As base layer is formed on the n-type GaAs collector layer. An emitter layer is formed such that it is arranged only in the intrinsic transistor region on the p.sup.+ -type Al.sub.x Ga.sub.l-x As base layer and constitutes a heterojunction together with the base layer. Design trade-off between the cutoff frequency and maximum oscillation frequency of the transistor is eliminated.

Abstract: A semiconductor light wave detector which has a first layer of a highly doped n-type semiconducting substrate, a second layer of a highly doped n-type semiconducting material, a third layer of a distinct intrinsic semiconducting material and a fourth layer of a highly doped n-type semiconducting material similar to the second layer. First and second electrical connections are provided to the fourth layer and to at least one of the first and second layers. A plurality of pairs of Dirac-delta doped monoatomic layers are in the third layer, with the first monoatomic layer of each pair being a layer of donors and with the second monoatomic layer of each pair being acceptors spaced from the donor layer and positioned on the side thereof facing the fourth layer.

Abstract: In an open-hole section formed in a silicon oxide layer, a polycrystalline silicon layer, which will become a lower layer of an emitter electrode, is deposited and arsenic ions are implanted into it. Next, on top of the polycrystalline silicon layer, another polycrystalline silicon layer, which will become an upper layer of the emitter electrode, is deposited and implanted with a high density of arsenic ions. Through heat treatment, an N-type emitter diffusion layer is formed inside a P-type intrinsic base diffusion layer. By constructing the emitter electrode with 2 layers, the lower layer and upper layer, and by optimizing the impurity density in each of the layers, the characteristic irregularities of a bipolar transistor having minute emitter contact holes are reduced, and it is possible to increase the allowance of the formation conditions of the open-hole section which connects a wiring layer and to reduce the emitter resistance.

Abstract: In order to simplify the structure of a power amplifying transistor and improve its high-frequency characteristics, a base electrode (7b) and a collector electrode (7c) are formed on the surface of such a power amplifying transistor, while an emitter electrode (7e) is formed on its rear surface. Since it is possible to easily ground the emitter electrode (7e) and use the base and collector electrodes (7b, 7c) as an input and an output respectively, the structure is simplified and no wiring pattern is required, whereby high-frequency characteristics can be improved.

Abstract: A lateral bipolar transistor and method of making which is compatible with making BICMOS circuits are disclosed. The method includes: Forming on a substrate of one conductivity type at least one layer of a semiconductor material of opposite conductivity type. Forming a first region of opposite conductivity type into one portion of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region.

Abstract: A heterojunction bipolar transistor has an n-type emitter layer of aluminum gallium arsenide and a beryllium doped base layer forming a heterojunction together with the n-type emitter layer, and the base layer is associated with a heavily doped carbon doped base region so that the beryllium content is restricted below the critical value for preventing the emitter layer from undesirable beryllium diffusion.

Abstract: Both homojunction and heterojunction bipolar transistor structures are fabricated in unique trenched configurations so as to better utilize their surface areas by employing both the vertical and horizontal portions of their base regions with equal effectiveness. An important advantage of the unique trenched configurations is that the base region of each trenched structure is of precisely the same thickness throughout--both vertical and horizontal portions. Consequently, the transit time for charge carriers to diffuse across the base region and the base transport factor are uniform because of the uniform base thickness. Moreover, the parasitic capacitance region of each trenched structure beneath base metallization contacts is only a small portion of the entire base-collector junction region.

Abstract: A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

Abstract: A semiconductor device has an active region composed of an impurity diffused region formed in a substrate. The impurity diffused region is divided into a plurality of impurity diffused sub-regions formed separately from each other in the substrate but electrically coupled to each other.

Abstract: An improved NPN transistor and method of building thereof includes: a P- substrate 50; a N+ buried region 52 provided therein; a N- epitaxial layer 56 deposited onto the N buried region; a P base diffusion region 66 in the N- epi layer; a N+ reach-through region 60 through the N- epi layer to the N+ buried layer to thereby define a collector; a N++ implant or diffusion region 102 provided in the P base diffusion region to thereby define an emitter; and a P++ implant region 74 provided around the N++ emitter implant region which thereby defines the extrinsic base of the transistor, wherein the P++ implant region extends through the P region into the N- epi layer and wherein the P++ implant region extends as close to the N++ emitter implant region as possible without encroaching on the emitter.

Abstract: The invention relates to an integrated circuit having a vertical transistor. According to the invention, a transistor having a current amplification .beta. considerably higher than a conventional transistor is obtained due to the fact that the emitter (5) of the transistor has a thickness and a doping level such that the diffusion length of the minority charge carriers injected vertically into the latter is greater than or equal to the thickness of the emitter (5) and the emitter contact region is so small that during operation the total current of minority charge carriers injected from the base into the emitter region is much smaller than the current density of minority carriers injected from the base into the emitter region under the emitter contact region multiplied by the total surface area of the emitter region.

Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.

Abstract: Buried layers of a second conductivity type are formed in a plurality of portions of a surface region of a semiconductor substrate of a first conductivity type, and an epitaxial layer of the first conductivity type is formed on the buried layers and the semiconductor substrate. A plurality of well regions of the second conductivity type are formed in the epitaxial layer in contact with the buried layers, and a region of the second conductivity type with a high impurity concentration is formed in one of the well regions in contact with the buried layers. A field insulating layer is formed on a surface region of the semiconductor substrate between the well regions. An impurity is ion-implanted in a portion substantially immediately below the field insulating film a plurality of times to form inversion preventing layers of the first conductivity type having a plurality of impurity concentration peaks. Active elements are formed in the epitaxial layer of the first conductivity type and the well regions.

Abstract: An optically bistable semiconductor device which has a doped or undoped gallium arsenide substrate and a series of alternating n-type and p-type Dirac-delta doped monoatomic layers formed on the substrate. Each Dirac-delta doped monoatomic layer is separated from the next adjacent Dirac-delta doped monoatomic layer by a layer of pure, undoped intrinsic semiconductor material such as gallium arsenide.

Abstract: An integrated circuit includes a lateral transistor which has emitter regions (7) and collector regions (8) of a first conductivity type laterally spaced apart and included in a region (4, 5) of a second conductivity type opposed to the first. The lateral space (4) of the region (4, 5) of the second type situated between the emitter (7) and collector (8) regions forms the base of the transistor, with the emitter region (7) having a depth and a doping level which are such that the diffusion length of the minority carriers injected vertically therein is greater than or equal to the width of the region, which region has an elongate shape in at least a longitudinal direction, while the lateral transistor has its contour surrounded by a deep insulating layer (12).

Abstract: In one embodiment of the invention, a P buried region is formed in an N epitaxial layer and isolated from a P substrate by an N buried region. P+ emitters and P+ collectors are formed in the surface of the N epitaxial layer (acting as a base). The P buried region acts as a catch diffusion for minority hole carriers injected into the epitaxial layer by the surface emitters that escape collection by the surface P+ collectors and which would otherwise be injected into the substrate. The N buried region effectively isolates the P buried region from the P substrate and further blocks any minority carriers from being injected into the substrate. The P buried region also prevents the formation of a parasitic PNP transistor to the substrate of the integrated device. This further reduces substrate current and thus further reduces the possibility of noise and latchup.