Abstract: A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source.

Abstract: An insulating film and a conducting film are formed in that order on an N type semiconductor substrate to form a capacitor structure of “conducting film—insulating film—semiconductor”; a heavily doped P region having a high impurity concentration is provided on the N type semiconductor substrate to contact a covered region which is covered with the conducting film; and furthermore a heavily doped N region for conducting an electrode on the semiconductor side is provided and connected with the heavily doped P region, resulting in quickly variance of the capacitance values in accordance with the voltage applied between the heavily doped N region and a terminal of the conducting film.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: The semiconductor device comprises a low-conductivity or insulating layer (5) on one surface of which is formed a conducting section (6) while the other face is provided with a hole- or electron-type semiconductor layer (1) with an ohmic contact. A semiconductor or metal layer (2) is provided on the surface of the semiconductor layer and with (1) forms a p-n junction or Schottky barrier with another ohmic contact. The choice of the alloy cross section and thickness of the layer (1) is restricted by the condition that said layer or part of it must be fully depleted by the basic charge carriers until breakdown of the p-n junction and/or the Schottky barrier when the latter is subjected to an external bias determined by the inequality shown in the application. The p-n junction and/or Schottky barrier can be formed with a non-homogeneous dopant section along a selected X direction on the surface of the layer (1).

Abstract: A voltage variable capacitor (10) fabricated on a semiconductor substrate (11) includes a gate structure (62) and a well (22) under the gate structure (62). A heavily doped buried layer (15) and a heavily doped contact region (31) in the semiconductor substrate (11) form a low resistance conduction path from the well (22) to a surface (17) of the semiconductor substrate (11). A multi-finger layout is used to construct the voltage variable capacitor (10). In operation, when a voltage applied across the voltage variable capacitor (10) changes, the width of depletion region in the well (22) changes, and the capacitance of the voltage variable capacitor (10) varies accordingly.

Abstract: When a variable capacitance diode device is formed on each of chips obtained by cutting off a wafer, the capacitance values of the diode devices formed on the chips disperse for each wafer due to change in the manufacturing process conditions. To reduced the dispersion in capacitance value of the diode devices, a plurality of variable capacitance diodes (10A, 10B and 10C) are formed on the same semiconductor chip (2) in such a way that the areas of the PN junctions (4A, 4B and 4C) of the respective diodes are different from each other. Further, only one variable capacitance diode (e.g., 10C) which can satisfy a predetermined strict standard is selected and connected to a terminal (11) for use.

Abstract: A varactor comprising a substrate of semiconductor material on which is grown both an electrostatic barrier having a first layer of material doped with donor impurities and a second layer of material doped with acceptor impurities and a depletable layer. In other embodiments of the present invention varactors are provided that include a plurality of barrier and depletable layer pairs grown in a serial arrangement.

Abstract: A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.

Abstract: A Schottky rectifier includes MOS-filled trenches and an anode electrode at a face of a semiconductor substrate and an optimally nonuniformly doped drift region therein which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage drop. The nonuniformly doped drift region contains a concentration of first conductivity type dopants therein which increases monotonically in a direction away from a Schottky rectifying junction formed between the anode electrode and the drift region. A profile of the doping concentration in the drift region is preferably a linear or step graded profile with a concentration of less than about 5.times.10.sup.16 cm.sup.-3 (e.g., 1.times.10.sup.16 cm.sup.-3) at the Schottky rectifying junction and a concentration of about ten times greater (e.g., 3.times.10.sup.17 cm.sup.-3) at a junction between the drift region and a cathode region. The thickness of the insulating regions (e.g., SiO.sub.

Abstract: A doping profile is disclosed for realizing a varactor diode that exhibits a high breakdown voltage V.sub.BR, e.g.,>100 volts, and a capacitance which has a bi-level characteristic. In particular, the capacitance has a C.sub.max level and a C.sub.min level. The doping profile includes two lightly doped regions and, between them, a third region with higher doping. The doping concentrations and widths of the first two regions substantially set the tuning ratio of C.sub.max /C.sub.min, and the doping concentration and width of the third region substantially sets the transition voltage V.sub.TR between the bi-level capacitances.

Abstract: A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.

Abstract: There is provided a variable capacitance diode device. The device comprises a semiconductor substrate of a first conductive type, an epitaxial layer of the first conductive type with a high specific resistance formed on the semiconductor substrate, a first diffusion layer of the first conductive type, in which impurities are more diffused than the epitaxial layer, formed in the epitaxial layer and a second diffusion layer of a second conductive type which forms a junction with the first diffusion layer. The first diffusion layer is formed in a hollow cylindrical body or a hollow square pole body, etc., so as to enlarge an outer peripheral area thereof.

Abstract: A varactor diode having a stepped capacitance-voltage profile, formed in heterostructural integrated circuit technology. Several layers in the diode structure have pulse doping to confine conduction in the diode to a sheet of charge that provides the stepped capacitance-voltage profile. The structural design of the diode may be modified to attain desired capacitance-voltage characteristics.

Abstract: A metal or silicide buried layer in MOS semiconductor devices provides a drain contact on the upper surface of the device with a greatly reduced resistance. The methods of manufacture include depositing the buried layer, rather than diffusing, so that interference with other components is greatly reduced and spacing between components is reduced to reduce the over-all size of the device.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.