Abstract: A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The output comparison diode unit may be arranged between the anode pad and the cathode pad. The temperature sensing unit may include a temperature sensing diode, and the output comparison diode unit may include a diode connected in inverse parallel to the temperature sensing diode.

Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

Abstract: Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

Abstract: A semiconductor structure includes a substrate having a seal ring region and a circuit region; one or more dielectric layers disposed on the substrate; a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.

Abstract: The semiconductor device includes a semiconductor layer having a main surface, a first semiconductor region of a first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a second semiconductor region of a second conductivity type formed in a surface layer portion of the first semiconductor region and forming a zener diode with the first semiconductor region, a third semiconductor region of the first conductivity type formed in the surface layer portion of the first semiconductor region separated from the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in a region between the second semiconductor region and the third semiconductor region in the surface layer portion of the first semiconductor region and having a second conductivity type impurity concentration less than a second conductivity type impurity concentration of the second semiconductor region, and an insulating layer formed on the main surface of the se

Abstract: Switch devices, such as Silicon Controlled Rectifier (SCR), DIAC, or TRIAC, on a semiconductor body are disclosed. P/N junctions can be built on a semiconductor body, such as polysilicon or active region body on an insulated substrate, with a first implant in one end and a second implant in the other end. The first and second implant regions are separated with a space. A silicide block layer can cover the space and overlap into both implant regions to construct P/N junctions in the interface.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a device portion disposed in the semiconductor substrate, and a junction terminal portion disposed in the semiconductor substrate and having an annular shape surrounding the device portion. The junction terminal portion includes first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The first semiconductor regions are adjacent to each other in a circumferential direction of the annular shape of the junction terminal portion, and have a width decreasing with progressing in a direction away from the device portion. The second semiconductor regions are disposed between the first semiconductor regions, and have a width increasing with progressing in the direction away from the device portion.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.

Abstract: A semiconductor component includes a two-sided semiconductor body, an inner zone with a basic doping of a first conduction type, and two semiconductor zones. The first zone, disposed between the first side and inner zone, is of the first conduction type with a doping concentration higher than that of the inner zone. The second zone, disposed between the second side and inner zone, is of a second conduction type complementary to the first type with a doping concentration higher than that of the inner zone. At least one first edge chamfer extends at a first angle to the extension plane of the transition from the second zone to the inner zone at least along the edge of the second zone and inner zone. At least one buried zone of the second conduction type is provided between the first zone and inner zone, and extends substantially parallel to the first zone.

Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.

Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.

Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.

Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.

Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.

Abstract: Apparatuses and systems for photon detection can include a first optical sensing structure structured to absorb light at a first optical wavelength; and a second optical sensing structure engaged with the first optical sensing structure to allow optical communication between the first and the second optical sensing structures. The second optical sensing structure can be structured to absorb light at a second optical wavelength longer than the first optical wavelength and to emit light at the first optical wavelength which is absorbed by the first optical sensing structure. Apparatuses and systems can include a bandgap grading region.

Abstract: An electro-static discharge protection circuit includes: a PNPN junction, a P-type side of the PNPN junction being coupled to a terminal, an N-type side of the PNPN junction being coupled to ground; and a P-type metal oxide semiconductor transistor, a source and a gate of the P-type metal oxide semiconductor transistor being coupled to an N-type side of a PN junction whose P-type side coupled to the ground, and a drain of the P-type metal oxide semiconductor transistor being coupled to the terminal.

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.

Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.

Abstract: A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: Provided are a light emitting device package and a method for fabricating the same. The light emitting device package comprises a substrate; a light emitting device on the substrate; a zener diode comprising a first conductive type impurity region and two second conductive type impurity regions, the first conductive type impurity region being disposed in the substrate, the two second conductive type impurity regions being separately disposed in two areas of the first conductive type impurity region; and a first electrode layer and a second electrode layer, each of them being electrically connected to the second conductive type impurity regions and the light emitting device.

Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.

Abstract: Provided are a light emitting device package and a method for fabricating the same. The light emitting device package comprises a substrate; a light emitting device on the substrate; a zener diode comprising a first conductive type impurity region and two second conductive type impurity regions, the first conductive type impurity region being disposed in the substrate, the two second conductive type impurity regions being separately disposed in two areas of the first conductive type impurity region; and a first electrode layer and a second electrode layer, each of them being electrically connected to the second conductive type impurity regions and the light emitting device.

Abstract: Techniques and apparatus for using single photon avalanche diode (SPAD) devices in various applications.

Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.

Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor layer and the metallization. The contact area includes at least one first semiconductor area that has a second doping density higher than the first doping density, and at least one second semiconductor area in the semiconductor layer. The second semiconductor area is in contact with the metallization and provides lower ohmic resistance to the metallization than a direct contact between the semiconductor layer and the metallization provides or would provide.

Abstract: There is provided a wiring board. The wiring board includes: a semiconductor substrate having a through hole and covered with an insulating film; a through electrode formed in the through hole; a first wiring connected to one end of the through electrode; and a second wiring connected to the other end of the through electrode. The semiconductor substrate includes: a semiconductor element and a first guard ring formed to surround the through hole. The semiconductor element includes a first conductivity-type impurity diffusion layer having a different conductivity-type from that of the semiconductor substrate and is electrically connected to the first wiring and the second wiring.

Abstract: A semiconductor device for surge protection having high surge resistance is provided.

Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

Abstract: A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.

Abstract: A semiconductor device comprising: a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.

Abstract: A semiconductor device has a semiconductor substrate including an n-type high impurity concentration layer inhibiting a depletion layer from spreading, an n-type low impurity concentration drift layer, and a p-type high impurity concentration layer forming a p-n main junction between the drift layer. In the active region, an effective current flows in the direction of the thickness of the substrate. The device has an inclined trench that cuts the p-n main junction at a positive bevel angle from the semiconductor substrate surface on the side of the n-type high impurity concentration layer to penetrate through the substrate for separating it into chips. In the device, along the sidewall of the inclined trench in the n-type drift layer, an n-type surface region is formed with an impurity concentration lower than that in the n-type drift layer.

Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction termination region formed to surround the junction forming region, and including a semiconductor region of a conductivity type different from the SiC layer formed as a substantially quadrangular doughnut ring, having two edges facing each other, each crossing a projection direction, which is obtained when the off direction is projected on the upper surface of the SiC layer, at a right angle, wherein a width of one of the two edges on an upper stream side of the off direction is L1, that of the other edge on a down stream side is L2, and a relation L1>L2 is satisfied.

Abstract: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type.

Abstract: In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a gate of the MOSFET. A second conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a drain of the MOSFET. A protection circuit is made of at least two diodes which are defined between the first conductive layer and the second conductive layer.

Abstract: The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.

Abstract: The present invention provides a constitution of n-type ohmic electrode suitable for n-type group III nitride semiconductor, and a forming method thereof for providing low contact resistivity. The n-type ohmic electrode is provided to comprise an alloy of aluminum and lanthanum or comprises lanthanum at the junction interface with the n-type group III nitride semiconductor. The method comprising forming a lanthanum-aluminum alloy layer at 300° C. or less to form an n-type ohmic electrode enriched in lanthanum at the junction interface.

Abstract: In a peripheral portion of an IGBT chip, an intermediate potential electrode (20) is provided between a field plate (14) and a field plate (15) on a field oxide film (13), to surround an IGBT cell. The intermediate potential electrode (20) is supplied with a prescribed intermediate potential between the potentials at an emitter electrode (10) and a channel stopper electrode (12) from intermediate potential applying means that is formed locally in a partial region on the chip peripheral portion.

Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.

Abstract: The present invention provides an avalanche photodiode capable of raising productivity. An n-type InP buffer layer, an n-type GaInAs light absorption layer, an n-type GaInAsP transition layer, an n-type InP electric field adjusting layer, an n-type InP avalanche intensifying layer, an n-type AlInAs window layer and a p-type GaInAs contact layer are grown in order on an n-type InP substrate. Next, Be is ion-injected into an annular area along the outer periphery of a light receiving area which is activated by heat treatment so as to form an inclined joint, to obtain a p-type peripheral area for preventing an edge break down. Further, Zn is selectively diffused thermally into the light receiving area until it reaches the n-type InP avalanche intensifying layer so as to form a p-type conductive area.

Abstract: A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed to prevent direct electrical contact between the field rings and the field plate such that the at least one field ring is capacitively coupled with the at least one field plate. Such a termination region may also include a polysilicon plate capacitively coupled with a diffusion region laterally spaced from the field rings, the polysilicon plate being located at an outer surface or directly under a passivation layer at an outer surface of the die. The termination region may also include floating field rings. The insulation layer may be a field oxide layer.

Abstract: In a semiconductor system 20 made up of multiple sublayers, a sublayer over the largest part of a cross-sectional area BC in the interior of the semiconductor system borders immediately on the first sublayer, while bordering on a second sublayer only in a comparatively narrow edge region of the cross-sectional area. The semiconductor system is characterized by a low bulk resistance and a high breakdown voltage in the edge region. In addition, a method for manufacturing this semiconductor system is specified.