With Means To Limit Area Of Breakdown (e.g., Guard Ring Having Higher Breakdown Voltage) Patents (Class 257/605)
  • Patent number: 10825808
    Abstract: The semiconductor device includes a semiconductor layer having a main surface, a first semiconductor region of a first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a second semiconductor region of a second conductivity type formed in a surface layer portion of the first semiconductor region and forming a zener diode with the first semiconductor region, a third semiconductor region of the first conductivity type formed in the surface layer portion of the first semiconductor region separated from the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in a region between the second semiconductor region and the third semiconductor region in the surface layer portion of the first semiconductor region and having a second conductivity type impurity concentration less than a second conductivity type impurity concentration of the second semiconductor region, and an insulating layer formed on the main surface of the se
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Toshiyuki Kanaya, Tsuyoshi Hosono
  • Patent number: 9324849
    Abstract: Switch devices, such as Silicon Controlled Rectifier (SCR), DIAC, or TRIAC, on a semiconductor body are disclosed. P/N junctions can be built on a semiconductor body, such as polysilicon or active region body on an insulated substrate, with a first implant in one end and a second implant in the other end. The first and second implant regions are separated with a space. A silicide block layer can cover the space and overlap into both implant regions to construct P/N junctions in the interface.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: April 26, 2016
    Inventor: Shine C. Chung
  • Patent number: 9082810
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a device portion disposed in the semiconductor substrate, and a junction terminal portion disposed in the semiconductor substrate and having an annular shape surrounding the device portion. The junction terminal portion includes first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The first semiconductor regions are adjacent to each other in a circumferential direction of the annular shape of the junction terminal portion, and have a width decreasing with progressing in a direction away from the device portion. The second semiconductor regions are disposed between the first semiconductor regions, and have a width increasing with progressing in the direction away from the device portion.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 9024412
    Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Fumio Tonomura, Hideo Ishii, Tsuyoshi Ota
  • Patent number: 9000538
    Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Murakawa
  • Patent number: 8946867
    Abstract: A semiconductor component includes a two-sided semiconductor body, an inner zone with a basic doping of a first conduction type, and two semiconductor zones. The first zone, disposed between the first side and inner zone, is of the first conduction type with a doping concentration higher than that of the inner zone. The second zone, disposed between the second side and inner zone, is of a second conduction type complementary to the first type with a doping concentration higher than that of the inner zone. At least one first edge chamfer extends at a first angle to the extension plane of the transition from the second zone to the inner zone at least along the edge of the second zone and inner zone. At least one buried zone of the second conduction type is provided between the first zone and inner zone, and extends substantially parallel to the first zone.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies Bipolar GmbH & Co. KG
    Inventors: Reiner Barthelmess, Hans-Joachim Schulze, Uwe Kellner-Werdehausen, Josef Lutz, Thomas Basler
  • Patent number: 8941207
    Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 27, 2015
    Assignee: University of Electronic Science and Technology
    Inventor: Xingbi Chen
  • Patent number: 8822316
    Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Atsuya Masada, Mitsuo Horie
  • Patent number: 8816321
    Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tadashi Takeoka, Yoshihiko Tani, Kazuya Araki, Yoshihiro Ueta
  • Patent number: 8742500
    Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: June 3, 2014
    Assignee: Fuji Electric Co., Ltd
    Inventor: Yasuhiko Onishi
  • Patent number: 8643104
    Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Shan Liao, An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang
  • Patent number: 8637875
    Abstract: Apparatuses and systems for photon detection can include a first optical sensing structure structured to absorb light at a first optical wavelength; and a second optical sensing structure engaged with the first optical sensing structure to allow optical communication between the first and the second optical sensing structures. The second optical sensing structure can be structured to absorb light at a second optical wavelength longer than the first optical wavelength and to emit light at the first optical wavelength which is absorbed by the first optical sensing structure. Apparatuses and systems can include a bandgap grading region.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 28, 2014
    Assignee: The Regents of the University of California
    Inventors: Hod Finkelstein, Sadik C. Esener, Yu-Hwa Lo, Kai Zhao, James Cheng, Sifang You
  • Patent number: 8633543
    Abstract: An electro-static discharge protection circuit includes: a PNPN junction, a P-type side of the PNPN junction being coupled to a terminal, an N-type side of the PNPN junction being coupled to ground; and a P-type metal oxide semiconductor transistor, a source and a gate of the P-type metal oxide semiconductor transistor being coupled to an N-type side of a PN junction whose P-type side coupled to the ground, and a drain of the P-type metal oxide semiconductor transistor being coupled to the terminal.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutoshi Ohta, Kenji Hashimoto
  • Patent number: 8492866
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Patent number: 8471293
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Patent number: 8415765
    Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 9, 2013
    Assignee: Panasonic Corporation
    Inventors: Atsuya Masada, Mitsuo Horie
  • Patent number: 8274080
    Abstract: A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hyun Han
  • Patent number: 8217436
    Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: July 10, 2012
    Assignee: STMicroelectronics (Research & Development) Ltd.
    Inventors: Robert K. Henderson, Justin Richardson
  • Patent number: 8217416
    Abstract: Provided are a light emitting device package and a method for fabricating the same. The light emitting device package comprises a substrate; a light emitting device on the substrate; a zener diode comprising a first conductive type impurity region and two second conductive type impurity regions, the first conductive type impurity region being disposed in the substrate, the two second conductive type impurity regions being separately disposed in two areas of the first conductive type impurity region; and a first electrode layer and a second electrode layer, each of them being electrically connected to the second conductive type impurity regions and the light emitting device.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: July 10, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Geun Ho Kim, Yong Seon Song, Yu Ho Won
  • Patent number: 8198651
    Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: June 12, 2012
    Assignee: Infineon Technologies AG
    Inventors: Gernot Langguth, Wolfgang Soldner, Cornelius Christian Russ
  • Patent number: 8188563
    Abstract: Techniques and apparatus for using single photon avalanche diode (SPAD) devices in various applications.
    Type: Grant
    Filed: July 21, 2007
    Date of Patent: May 29, 2012
    Assignee: The Regents of the University of California
    Inventors: Hod Finkelstein, Sadik C. Esener
  • Patent number: 8188507
    Abstract: Provided are a light emitting device package and a method for fabricating the same. The light emitting device package comprises a substrate; a light emitting device on the substrate; a zener diode comprising a first conductive type impurity region and two second conductive type impurity regions, the first conductive type impurity region being disposed in the substrate, the two second conductive type impurity regions being separately disposed in two areas of the first conductive type impurity region; and a first electrode layer and a second electrode layer, each of them being electrically connected to the second conductive type impurity regions and the light emitting device.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: May 29, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Geun Ho Kim, Yong Seon Song, Yu Ho Won
  • Patent number: 8138520
    Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Mark Duskin, Suem Ping Loo, Ali Salih
  • Patent number: 8084815
    Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: December 27, 2011
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Jae-gil Lee, Jin-young Jung, Ho-cheol Jang, Chong-man Yun
  • Patent number: 8078998
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 13, 2011
    Assignee: Infineon Technologies AG
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Patent number: 8035195
    Abstract: A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor layer and the metallization. The contact area includes at least one first semiconductor area that has a second doping density higher than the first doping density, and at least one second semiconductor area in the semiconductor layer. The second semiconductor area is in contact with the metallization and provides lower ohmic resistance to the metallization than a direct contact between the semiconductor layer and the metallization provides or would provide.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 11, 2011
    Assignee: Infineon Technologies AG
    Inventors: Franz Josef Niedernostheide, Manfred Pfaffenlehner, Hans-Joachim Schulze
  • Patent number: 8026576
    Abstract: There is provided a wiring board. The wiring board includes: a semiconductor substrate having a through hole and covered with an insulating film; a through electrode formed in the through hole; a first wiring connected to one end of the through electrode; and a second wiring connected to the other end of the through electrode. The semiconductor substrate includes: a semiconductor element and a first guard ring formed to surround the through hole. The semiconductor element includes a first conductivity-type impurity diffusion layer having a different conductivity-type from that of the semiconductor substrate and is electrically connected to the first wiring and the second wiring.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 27, 2011
    Assignees: Shinko Electric Industries Co., Ltd., Asahi Kasei Microdevices Corporation
    Inventors: Kei Murayama, Shinji Nakajima
  • Patent number: 8004041
    Abstract: A semiconductor device for surge protection having high surge resistance is provided.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: August 23, 2011
    Assignee: Panasonic Corporation
    Inventor: Kazuhiro Ohnishi
  • Publication number: 20110175199
    Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.
    Type: Application
    Filed: January 18, 2010
    Publication date: July 21, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 7821099
    Abstract: A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Publication number: 20100244194
    Abstract: A semiconductor device comprising: a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions.
    Type: Application
    Filed: February 17, 2010
    Publication date: September 30, 2010
    Inventors: Atsuya MASADA, Mitsuo Horie
  • Patent number: 7804143
    Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: September 28, 2010
    Assignee: Intersil Americas, Inc.
    Inventors: Stephen Joseph Gaul, Michael D. Church, Brent R. Doyle
  • Patent number: 7781786
    Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: August 24, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7772677
    Abstract: A semiconductor device has a semiconductor substrate including an n-type high impurity concentration layer inhibiting a depletion layer from spreading, an n-type low impurity concentration drift layer, and a p-type high impurity concentration layer forming a p-n main junction between the drift layer. In the active region, an effective current flows in the direction of the thickness of the substrate. The device has an inclined trench that cuts the p-n main junction at a positive bevel angle from the semiconductor substrate surface on the side of the n-type high impurity concentration layer to penetrate through the substrate for separating it into chips. In the device, along the sidewall of the inclined trench in the n-type drift layer, an n-type surface region is formed with an impurity concentration lower than that in the n-type drift layer.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: August 10, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 7667242
    Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 23, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: John V. Veliadis, Eric Jonathan Stewart, Megan Jean McCoy, Li-Shu Chen, Ty Richard McNutt
  • Publication number: 20100019295
    Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 28, 2010
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventors: Robert K. Henderson, Justin Richardson
  • Patent number: 7649213
    Abstract: A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction termination region formed to surround the junction forming region, and including a semiconductor region of a conductivity type different from the SiC layer formed as a substantially quadrangular doughnut ring, having two edges facing each other, each crossing a projection direction, which is obtained when the off direction is projected on the upper surface of the SiC layer, at a right angle, wherein a width of one of the two edges on an upper stream side of the off direction is L1, that of the other edge on a down stream side is L2, and a relation L1>L2 is satisfied.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: January 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Hatakeyama, Takashi Shinohe
  • Patent number: 7638857
    Abstract: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: December 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yen Hwang, Shu-Hsuan Su, Tien-Hao Tang
  • Patent number: 7626214
    Abstract: In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a gate of the MOSFET. A second conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a drain of the MOSFET. A protection circuit is made of at least two diodes which are defined between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: December 1, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyoshi Kobayashi
  • Patent number: 7612371
    Abstract: The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: November 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ishtiaq Ahsan, Christine M. Bunke, Stephen E. Greco
  • Patent number: 7598593
    Abstract: The present invention provides a constitution of n-type ohmic electrode suitable for n-type group III nitride semiconductor, and a forming method thereof for providing low contact resistivity. The n-type ohmic electrode is provided to comprise an alloy of aluminum and lanthanum or comprises lanthanum at the junction interface with the n-type group III nitride semiconductor. The method comprising forming a lanthanum-aluminum alloy layer at 300° C. or less to form an n-type ohmic electrode enriched in lanthanum at the junction interface.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: October 6, 2009
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 7582918
    Abstract: In a peripheral portion of an IGBT chip, an intermediate potential electrode (20) is provided between a field plate (14) and a field plate (15) on a field oxide film (13), to surround an IGBT cell. The intermediate potential electrode (20) is supplied with a prescribed intermediate potential between the potentials at an emitter electrode (10) and a channel stopper electrode (12) from intermediate potential applying means that is formed locally in a partial region on the chip peripheral portion.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: September 1, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tetsuo Takahashi
  • Patent number: 7547586
    Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: June 16, 2009
    Assignee: Northrop Grumman Corp
    Inventor: Li-Shu Chen
  • Patent number: 7538367
    Abstract: The present invention provides an avalanche photodiode capable of raising productivity. An n-type InP buffer layer, an n-type GaInAs light absorption layer, an n-type GaInAsP transition layer, an n-type InP electric field adjusting layer, an n-type InP avalanche intensifying layer, an n-type AlInAs window layer and a p-type GaInAs contact layer are grown in order on an n-type InP substrate. Next, Be is ion-injected into an annular area along the outer periphery of a light receiving area which is activated by heat treatment so as to form an inclined joint, to obtain a p-type peripheral area for preventing an edge break down. Further, Zn is selectively diffused thermally into the light receiving area until it reaches the n-type InP avalanche intensifying layer so as to form a p-type conductive area.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: May 26, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiji Yagyu, Eitaro Ishimura, Masaharu Nakaji
  • Patent number: 7525178
    Abstract: A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed to prevent direct electrical contact between the field rings and the field plate such that the at least one field ring is capacitively coupled with the at least one field plate. Such a termination region may also include a polysilicon plate capacitively coupled with a diffusion region laterally spaced from the field rings, the polysilicon plate being located at an outer surface or directly under a passivation layer at an outer surface of the die. The termination region may also include floating field rings. The insulation layer may be a field oxide layer.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: April 28, 2009
    Assignee: International Rectifier Corporation
    Inventor: Lawrence Kulinsky
  • Patent number: 7521774
    Abstract: In a semiconductor system 20 made up of multiple sublayers, a sublayer over the largest part of a cross-sectional area BC in the interior of the semiconductor system borders immediately on the first sublayer, while bordering on a second sublayer only in a comparatively narrow edge region of the cross-sectional area. The semiconductor system is characterized by a low bulk resistance and a high breakdown voltage in the edge region. In addition, a method for manufacturing this semiconductor system is specified.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: April 21, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Dana Keppeler
  • Patent number: 7517762
    Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
  • Patent number: 7511357
    Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: March 31, 2009
    Assignee: Force-MOS Technology Corporation
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7485947
    Abstract: A zener diode circuit includes a semiconductor substrate having an N-doped region and a P-doped region that form a PN junction. The N-doped region and the P-doped region have areas with widths that decrease as the N-doped region and the P-doped region approach the PN junction. The zener diode circuit also includes a transistor that provides current to the zener diode, and circuitry that detects a state of the zener diode.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: February 3, 2009
    Assignee: Austriamicrosystems AG
    Inventor: Franz Unterleitner
  • Patent number: 7468533
    Abstract: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: December 23, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Robert J. Hanson, Alex Schrinsky, Terry McDaniel