For Compound Semiconductor (e.g., Deep Level Dopant) Patents (Class 257/609)
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Patent number: 11634340Abstract: Proposed are a layered Group III-V arsenic compound, a Group III-V nanosheet that may be prepared using the same, and an electrical device including the materials. There is proposed a layered compound having a composition represented by [Formula 1] Mx-mAyAsz (Where M is at least one of Group I elements, A is at least one of Group III elements, x, y, and z are positive numbers which are determined according to stoichiometric ratios to ensure charge balance when m is 0, and 0<m<x).Type: GrantFiled: December 3, 2020Date of Patent: April 25, 2023Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Woo-young Shim, Sang-jin Choi, Tae-young Kim
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Patent number: 10453994Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs.Type: GrantFiled: April 10, 2019Date of Patent: October 22, 2019Assignee: Lumeova, Inc.Inventors: Mohammad Ali Khatibzadeh, Arunesh Goswami
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Patent number: 10312410Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a light-emitting diode (LED) includes a substrate, a carrier confinement (CC) region positioned over the substrate, an active region positioned over the CC region, and an electron blocking layer (EBL) positioned over the active region. The CC region includes a first CC layer comprising aluminum gallium arsenide and a second CC layer position over the first CC layer. The second CC layer and the electron blocking layer (EBL) also each include aluminum gallium arsenide. The active region is configured to have a transient response time of less than 500 picoseconds (ps).Type: GrantFiled: December 29, 2017Date of Patent: June 4, 2019Assignee: LUMEOVA, INC.Inventors: Mohammad Ali Khatibzadeh, Arunesh Goswami
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Patent number: 10263146Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs.Type: GrantFiled: January 5, 2018Date of Patent: April 16, 2019Assignee: LUMEOVA, INC.Inventors: Mohammad Ali Khatibzadeh, Arunesh Goswami
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Patent number: 9576819Abstract: A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.Type: GrantFiled: June 17, 2015Date of Patent: February 21, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Benjamin Colombeau, Kevin Jones, Aaron Lind
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Patent number: 9305776Abstract: Disclosed is a gallium nitride crystal substrate having a top surface, a bottom surface, regions of higher oxygen concentrations measured by SIMS, and other regions of lower oxygen concentrations measured by SIMS. The top surface is a C-plane surface. The ratio of the highest oxygen concentration to the lowest oxygen concentration is equal to or more than fifty.Type: GrantFiled: December 9, 2014Date of Patent: April 5, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kensaku Motoki, Masaki Ueno
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Publication number: 20150053997Abstract: A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other.Type: ApplicationFiled: October 31, 2014Publication date: February 26, 2015Inventors: CHUN-JU TUN, YI-CHAO LIN, CHEN-FU CHIANG, CHENG-HUANG KUO
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Patent number: 8946864Abstract: Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure. The film comprises a metal having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include metal ions that coalesce into a substantially continuous, electrically conductive metal layer, or that undergo covalent bonding, whereas in the absence of the embedded structure the metal ions instead may be free to diffuse through the substrate. The embedded structure may control the diffusion of the metal through the substrate and/or the reaction of the metal within the substrate.Type: GrantFiled: March 16, 2011Date of Patent: February 3, 2015Assignee: The Aerospace CorporationInventors: Margaret H. Abraham, David P. Taylor
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Patent number: 8933538Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained.Type: GrantFiled: January 3, 2014Date of Patent: January 13, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Masaki Ueno
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Publication number: 20140346638Abstract: The present invention relates to a single-crystalline aluminum nitride wherein a carbon concentration is 1×1014 atoms/cm3 or more and less than 3×1017 atoms/cm3, a chlorine concentration is 1×1014 to 1×1017 atoms/cm3, and an absorption coefficient at 265 nm wavelength is 40 cm?1 or less.Type: ApplicationFiled: December 22, 2011Publication date: November 27, 2014Applicants: TOKUYAMA CORPORATION, C/O NATIONAL UNIVERSITY CORPORATION TOKYOInventors: Akinori Koukitu, Yoshinao Kumagai, Toru Nagashima, Yuki Hiraren
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Publication number: 20140284768Abstract: A semiconductor structure comprising a first semiconductor layer, a bulk semiconductor layer, an insulation layer between the first semiconductor layer and the bulk semiconductor layer, a first implanted region that is at least partially within the insulation layer; and a second doped region that is at least partially within the bulk semiconductor layer, wherein the first implanted region has an implant profile that shows a maximum within the insulation layer and a tail extending within the bulk semiconductor layer so as to inhibit the diffusion of a second doping material of the second doped region within the insulation layer.Type: ApplicationFiled: November 13, 2012Publication date: September 25, 2014Applicant: SOITECInventor: Konstantin Bourdelle
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Patent number: 8836141Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.Type: GrantFiled: April 24, 2013Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hwa Chi, Tai-Chun Huang, Chih-Hsiang Yao
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Patent number: 8829489Abstract: A nitride semiconductor template includes a substrate, and a group III nitride semiconductor layer formed on the substrate and including a Si-doped layer doped with Si as an uppermost layer thereof. The group III nitride semiconductor layer has a total thickness of not less than 4 ?m and not more than 10 ?m. The Si-doped layer includes a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×1017 cm?3 and not more than 5×1017 cm?3 at the outermost surface of the group III nitride semiconductor layer.Type: GrantFiled: December 13, 2012Date of Patent: September 9, 2014Assignee: Hitachi Metals, Ltd.Inventors: Taichiroo Konno, Hajime Fujikura
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Patent number: 8772878Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.Type: GrantFiled: January 31, 2012Date of Patent: July 8, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
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Patent number: 8703596Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.Type: GrantFiled: September 11, 2012Date of Patent: April 22, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Naoyoshi Tamura
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Publication number: 20140001603Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AtGaAs are also amenable to beneficial processes described herein.Type: ApplicationFiled: September 3, 2013Publication date: January 2, 2014Applicant: ATMEL CORPORATIONInventors: Darwin Gene Enicks, John Chaffee, Damian A. Carver
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Patent number: 8604591Abstract: A nitride-based semiconductor device includes a p-type AldGaeN layer 25 whose growing plane is an m-plane and an electrode 30 provided on the p-type AldGaeN layer 25. The AldGaeN layer 25 includes a p-AldGaeN contact layer 26 that is made of an AlxGayInzN (x+y+z=1, x?0, y>0, z?0) semiconductor, which has a thickness of not less than 26 nm and not more than 60 nm. The p-AldGaeN contact layer 26 includes a body region 26A which contains Mg of not less than 4×1019 cm?3 and not more than 2×1020 cm?3 and a high concentration region 26B which is in contact with the electrode 30 and which has a Mg concentration of not less than 1×1021 cm?3.Type: GrantFiled: March 6, 2012Date of Patent: December 10, 2013Assignee: Panasonic CorporationInventors: Toshiya Yokogawa, Ryou Kato, Naomi Anzue
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Publication number: 20130320478Abstract: System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shiu-Ko JangJian, Kei-Wei Chen, Chi-Cherng Jeng, Min Hao Hong
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Patent number: 8502284Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.Type: GrantFiled: June 30, 2009Date of Patent: August 6, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Naoyoshi Tamura
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Patent number: 8471307Abstract: An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.Type: GrantFiled: June 11, 2009Date of Patent: June 25, 2013Assignee: Texas Instruments IncorporatedInventors: Rajesh B. Khamankar, Haowen Bu, Douglas Tad Grider
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Publication number: 20130153858Abstract: A nitride semiconductor template includes a substrate, and a group III nitride semiconductor layer formed on the substrate and including a Si-doped layer doped with Si as an uppermost layer thereof. The group III nitride semiconductor layer has a total thickness of not less than 4 ?m and not more than 10 ?m. The Si-doped layer includes a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×1017 cm?3 and not more than 5×1017 cm?3 at the outermost surface of the group III nitride semiconductor layer.Type: ApplicationFiled: December 13, 2012Publication date: June 20, 2013Applicant: HITACHI CABLE, LTD.Inventor: HITACHI CABLE, LTD.
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Patent number: 8421190Abstract: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm?3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.Type: GrantFiled: October 7, 2010Date of Patent: April 16, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takuji Okahisa, Hideaki Nakahata, Seiji Nakahata
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Publication number: 20120299155Abstract: Semiconductor devices are formed with a thin layer of fully strain relaxed epitaxial silicon germanium on a substrate. Embodiments include forming a silicon germanium (SiGe) epitaxial layer on a semiconductor substrate, implanting a dopant into the SiGe epitaxial layer, and annealing the implanted SiGe epitaxial layer.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventor: Jinping Liu
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Patent number: 8253220Abstract: A nitride semiconductor device includes a first nitride semiconductor layer formed on a substrate, a defect induced layer formed on the first nitride semiconductor layer, and a second nitride semiconductor layer formed on the defect induced layer, contacting the defect induced layer, and having an opening through which the defect induced layer is exposed. The defect induced layer has a higher crystal defect density than those of the first and second nitride semiconductor layers.Type: GrantFiled: July 11, 2011Date of Patent: August 28, 2012Assignee: Panasonic CorporationInventors: Ryo Kajitani, Satoshi Tamura, Hideki Kasugai
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Publication number: 20120187418Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si {111} crystal plane. Since the semiconductor fin exhibits better surface quality and less crystal defects, it is favorable for manufacturing FINFET.Type: ApplicationFiled: March 4, 2011Publication date: July 26, 2012Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
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Publication number: 20120168811Abstract: A nitride-based semiconductor device includes a p-type AldGaeN layer 25 whose growing plane is an m-plane and an electrode 30 provided on the p-type AldGaeN layer 25. The AldGaeN layer 25 includes a p-AldGaeN contact layer 26 that is made of an AlxGayInzN (x+y+z=1, x?0, y>0, z?0) semiconductor, which has a thickness of not less than 26 nm and not more than 60 nm. The p-AldGaeN contact layer 26 includes a body region 26A which contains Mg of not less than 4×1019 cm?3 and not more than 2×1020 cm?3 and a high concentration region 26B which is in contact with the electrode 30 and which has a Mg concentration of not less than 1×1021 cm?3.Type: ApplicationFiled: March 6, 2012Publication date: July 5, 2012Applicant: PANASONIC CORPORATIONInventors: Toshiya YOKOGAWA, Ryou KATO, Naomi ANZUE
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Patent number: 8212260Abstract: To provide a p-type semiconductor material having a band matching with a hole injection layer and suitable for an anode electrode that can be formed on a glass substrate or a polymer substrate, and to provide a semiconductor device. In the p-type semiconductor material, 1×1018 to 5×1020 cm?3 of Ag is contained in a compound containing Zn and Se, and the semiconductor device includes a substrate and a p-type electrode layer arranged on this substrate and having the aforementioned p-type semiconductor material.Type: GrantFiled: September 28, 2007Date of Patent: July 3, 2012Assignee: Hoya CorporationInventors: Masahiro Orita, Takashi Narushima, Hiroaki Yanagida
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Patent number: 8183668Abstract: A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m3/2.Type: GrantFiled: May 27, 2010Date of Patent: May 22, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventor: Akihiro Hachigo
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Patent number: 8154084Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.Type: GrantFiled: May 28, 2009Date of Patent: April 10, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
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Patent number: 8106483Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.Type: GrantFiled: March 29, 2011Date of Patent: January 31, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Jung-Yu Hsieh, Ling-Wu Yang
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Publication number: 20110309400Abstract: A nitride semiconductor device includes a first nitride semiconductor layer having a C-plane as a growth surface, and unevenness in an upper surface; and a second nitride semiconductor layer formed on the first nitride semiconductor layer to be in contact with the unevenness, and having p-type conductivity. The second nitride semiconductor layer located directly on a sidewall of the unevenness has a p-type carrier concentration of 1×1018/cm3 or more.Type: ApplicationFiled: September 1, 2011Publication date: December 22, 2011Applicant: PANASONIC CORPORATIONInventors: Yasuyuki FUKUSHIMA, Tetsuzo Ueda
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Publication number: 20110084363Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.Type: ApplicationFiled: November 24, 2010Publication date: April 14, 2011Inventors: Keiji ISHIBASHI, Fumitake NAKANISHI
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Patent number: 7919831Abstract: The present invention is a nitride semiconductor device including an n-type gallium nitride single crystal substrate, an epitaxially grown nitride film on the substrate, and electrodes deposited on a top and a bottom of the substrate. In order to produce the substrate, oxygen is doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing a faceted C-plane gallium nitride bulk crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the C-plane gallium nitride bulk crystal, and eliminating the seed crystal from the bulk crystal.Type: GrantFiled: January 5, 2010Date of Patent: April 5, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Masaki Ueno
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Patent number: 7898062Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: GrantFiled: April 9, 2010Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7884354Abstract: Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate comprising an insulative surface region wherein a concentration of dopant in the insulative surface region is less than a concentration of dopant in the semiconductor substrate outside of the insulative surface region and a thin film of germanium coupled to the insulative surface region of the semiconductor substrate wherein the thin film of germanium and the insulative surface region are simultaneously formed by oxidation anneal of a thin film of silicon germanium (Si1-xGex) deposited to the semiconductor substrate wherein x is a value between 0 and 1 that provides a relative amount of silicon and germanium in the thin film of Si1-xGex.Type: GrantFiled: July 31, 2008Date of Patent: February 8, 2011Assignee: Intel CorporationInventors: Ravi Pillarisetty, Been-Yih Jin, Willy Rachmady, Marko Radosavljevic
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Patent number: 7872285Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.Type: GrantFiled: March 1, 2006Date of Patent: January 18, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
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Patent number: 7847313Abstract: A group III-V nitride-based semiconductor substrate is formed of a group III-V nitride-based semiconductor single crystal containing an n-type impurity. The single crystal has a periodical change in concentration of the n-type impurity in a thickness direction of the substrate. The periodical change has a minimum value in concentration of the n-type impurity not less than 5×1017 cm?3 at an arbitrary point in plane of the substrate.Type: GrantFiled: March 12, 2007Date of Patent: December 7, 2010Assignee: Hitachi Cable, Ltd.Inventor: Masatomo Shibata
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Patent number: 7834422Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallized to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.Type: GrantFiled: May 18, 2005Date of Patent: November 16, 2010Assignee: Qucor Pty. Ltd.Inventors: Soren Andresen, Andrew Steven Dzurak, Eric Gauja, Sean Hearne, Toby Felix Hopf, David Norman Jamieson, Mladen Mitic, Steven Prawer, Changyi Yang
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Publication number: 20100193838Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Inventor: Paul A. Farrar
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Patent number: 7705429Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: GrantFiled: February 2, 2009Date of Patent: April 27, 2010Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7671358Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.Type: GrantFiled: September 4, 2007Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Nick Lindert, Mitchell C. Taylor
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Patent number: 7667298Abstract: Oxygen is doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases to the seed crystal, growing a non-C-plane gallium nitride crystal on the seed crystal and allowing oxygen to infiltrate via a non-C-plane surface to the growing crystal. Otherwise, oxygen is doped into the crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases to the C-plane seed crystal or the foreign seed crystal, growing a faceted C-plane gallium nitride crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the crystal and allowing oxygen to infiltrate via the non-C-plane facets to the crystal.Type: GrantFiled: November 20, 2008Date of Patent: February 23, 2010Assignee: Sumitomo Electric Industries Ltd.Inventors: Kensaku Motoki, Masaki Ueno
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Publication number: 20100025822Abstract: Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate comprising an insulative surface region wherein a concentration of dopant in the insulative surface region is less than a concentration of dopant in the semiconductor substrate outside of the insulative surface region and a thin film of germanium coupled to the insulative surface region of the semiconductor substrate wherein the thin film of germanium and the insulative surface region are simultaneously formed by oxidation anneal of a thin film of silicon germanium (Si1-xGex) deposited to the semiconductor substrate wherein x is a value between 0 and 1 that provides a relative amount of silicon and germanium in the thin film of Si1-xGex.Type: ApplicationFiled: July 31, 2008Publication date: February 4, 2010Inventors: Ravi Pillarisetty, Been-Yih Jin, Willy Rachmady, Marko Radosavljevic
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Patent number: 7629670Abstract: In a radiation-emitting semiconductor component with a layer structure comprising an n-doped confinement layer, a p-doped confinement layer, and an active, photon-emitting layer disposed between the n-doped confinement layer and the p-doped confinement layer, it is provided according to the invention that the n-doped confinement layer is doped with a first n-dopant (or two mutually different n-dopants) for producing high active doping and a sharp doping profile, and the active layer is doped with only one second n-dopant, different from the first dopant, for improving the layer quality of the active layer.Type: GrantFiled: June 25, 2004Date of Patent: December 8, 2009Assignee: Osram Opto Semiconductors GmbHInventors: Rainer Butendeich, Norbert Linder, Bernd Mayer, Ines Pietzonka
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Patent number: 7615804Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.Type: GrantFiled: January 3, 2005Date of Patent: November 10, 2009Assignee: Nichia Chemical Industries, Ltd.Inventors: Shinichi Nagahama, Masayuki Senoh, Shuji Nakamura
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Publication number: 20090230513Abstract: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded.Type: ApplicationFiled: November 15, 2007Publication date: September 17, 2009Applicant: SAMSUNG CORNING PRECISION GLASS CO., LTD.Inventors: Young Zo Yoo, Hyun Min Shin, Jun Sung Choi
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Publication number: 20090194796Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.Type: ApplicationFiled: March 1, 2006Publication date: August 6, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
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Publication number: 20090166806Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.Type: ApplicationFiled: February 2, 2009Publication date: July 2, 2009Inventor: Paul A. Farrar
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Publication number: 20090108407Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal.Type: ApplicationFiled: November 20, 2008Publication date: April 30, 2009Inventors: Kensaku Motoki, Masaki Ueno
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Publication number: 20090039469Abstract: The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better device performance and higher yield. The method described herein involves depositing a ceramic layer that contains the desired impurity and a certain element such as oxygen (in the form of oxide), or other elements/compounds that draw out the silicon and carbon atoms from the surface region of the SiC leaving behind carbon and silicon vacancies which then allow the external impurity to diffuse into the SiC more easily. In another embodiment, the deposited layer also has carbon atoms that discourage carbon from escaping from the SiC, thus generating a surface region of excess carbon in addition to the silicon vacancies.Type: ApplicationFiled: July 25, 2008Publication date: February 12, 2009Inventors: Chin-Che Tin, Adetayo Victor Adedeji, Ilkham Gafurovich Atabayev, Bakhtiyar Gafurovich Atabaev, Tojiddin Mutalovich Saliev, Erkin Nurovich Bakhranov, Mingyu Li, Balapuwaduge Suwan Pathum Mendis, Ayayi Claude Ahyi