Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing a faceted C-plane gallium nitride crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the C-plane gallium nitride crystal and allowing oxygen to infiltrate via the non-C-plane facets to the gallium nitride crystal.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: It is an object of the present invention to provide an epitaxial wafer with fewer pit defects in the epitaxial layer of a silicon monocrystalline wafer that has been doped with arsenic. Pit defects tend to occur when gas etching is performed prior to epitaxial film formation, but this tendency is reversed and a sound epitaxial layer is obtained by setting the crystal plane orientation to (100) and specifying the range of the tilt angle for the angle ? in the [001] direction or [001] direction or the angle ? in the [010] direction or [010] direction with respect to the [100] axis.

Abstract: The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate.

Abstract: A method of disordering a layer of an optoelectronic device including; growing a plurality of lower layers; introducing an isoelectronic surfactant; growing a layer; allowing the surfactant to desorb; and growing subsequent layers all performed at a low pressure of 25 torr.

Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III–V compound, i.e., an Al-III–V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III–V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III–V layer comprises InAlAs:O or InAlAs:O:Fe.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrate via a non-C-plane surface to the growing gallium nitride crystal. Otherwise, oxygen can be doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing a faceted C-plane gallium nitride crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the C-plane gallium nitride crystal and allowing oxygen to infiltrate via the non-C-plane facets to the gallium nitride crystal.

Abstract: Ferromagnetic semiconductor-based compositions, systems and methods that enable studies of the dynamics and magnetoresistance of individual magnetic domain walls, and which provide enhanced magnetic switching effects relative to metallic ferromagnets. Aspects of the present invention are enabled by recent studies of the Giant Planar Hall effect (GPHE), and in particular GPHE in (Ga,Mn)As—based devices. The GPHE generally originates from macro- and micromagnetic phenomena involving single domain reversals. The GPHE-induced resistance change in multiterminal, micron-scale structures patterned from (Ga,Mn)As can be as large as about 100?, four orders of magnitude greater than analogous effects previously observed in metallic ferromagnets. Accordingly, recent data provide sufficient resolution to enable real-time observations of the nucleation and field-induced propagation of individual magnetic domain walls within such monocrystalline devices.

Abstract: A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semi-conductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that the interstitial gallium does not diffuse to the base layer and thus does not cause the beryllium to be displaced and diffused. Instead of doping with phosphorus, a layer including phosphorus can also be utilized.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) with

Abstract: A heterojunction bipolar transistor (HBT), having a substrate formed of indium phosphide (InP), and having emitter, base and collector layers formed over the substrate such that the base layer is disposed between the emitter and collector layers. The collector layer formed from InGaAs, and the collector layer being doped n-type. The emitter layer formed from InP, and the emitter layer being doped n-type. The base layer formed of indium gallium arsenide (InGaAs) and grown by MOCVD, the base layer being tensile strained and graded, and the base layer being doped p-type with carbon. A lattice mismatch, for at least a portion of the base layer, between the substrate and the base material is greater than 0.2%.

Abstract: Fault remediation functions are embodied in a semiconductor structure in which high quality epitaxial layers of monocrystalline materials are made to overlie monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Fault remediation is carried out in one instance by recognizing the presence of a fault and in another instance by providing fault correction.

Abstract: The present invention is an electronic structure having a buffer layer with a short average carrier lifetime, at least about 1000 Å thick with an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrated circuit would otherwise be susceptible to soft errors, due to its configuration, its clock speed, its use environment, or a combination of these factors. In a preferred embodiment, the preferably high recombination rate buffer layer is an LT GaAs or GaAs:Er buffer layer.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: Disclosed is a compound semiconductor field effect transistor. The compound semiconductor field effect transistor has a charge absorption layer and a semiconductor laminated structure. The charge absorption layer includes a compound semiconductor layer of a first conductive type formed in a part of a compound semiconductor substrate having a semi-insulating layer. The semiconductor laminated structure includes at least an active layer including a compound semiconductor layer of a second conductive type epitaxially grown so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed. A source electrode is formed on the semiconductor laminated structure, being electrically connected to the charge absorption layer.

Abstract: A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, boron ions are implanted on the rear surface to form a defect-rich layer having carrier recombination centers.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: A GaAs single crystal substrate and an epitaxial wafer using the same suppress the generation of slips during growth of the epitaxial layer, and improve the breakdown withstanding characteristic of devices fabricated on such substrates. The GaAs single crystal substrate has a mean dislocation density in plane of at most 2×104 cm−2, a carbon concentration of 2.5 to 20.0×1015 cm−3, a boron concentration of 2.0 to 20.0×1016 cm−3, an impurity concentration other than carbon and boron of at most 1×1017 cm−3, an EL2 concentration of 5.0 to 10.0×1015 cm−3, resistivity of 1.0 to 5.0×108 &OHgr;·cm and a mean residual strain measured by photoelastic analysis of at most 1.0×10−5.

Abstract: An ohmic contact including a gallium arsenide substrate having an epitaxially grown crystalline layer of indium arsenide on the substrate. The crystalline material and the substrate define an interface, layers are n-doped with silicon close to the interface.

Abstract: A p-type semiconductor composed basically of an Ib-IIIb-VIb.sub.2 group compound semiconductor (especially CuInS.sub.2) which is improved in carrier concentration and has advantages in manufacture and performance. In order to obtain the p-type semiconductor mentioned above, p-type CuInS.sub.2 is formed by adding both P (p-type impurity) and Sn (n-type impurity) to CuInS.sub.2. The carrier concentration of the p-type semiconductor is 5.times.10.sup.17 cm.sup.-3 which is larger than the value (5.times.10.sup.16 cm.sup.-3) obtained when P and In are added or another value (3.times.10.sup.15 cm.sup.-3) obtained when only P is added. A thin film solar cell characterized by a glass substrate (2), an Mo electrode (1), a p-type semiconductor layer (3), an n-type semiconductor layer composed of a CdS layer (4), and an ITO electrode (5) is manufactured by using the CuInS.sub.2 layer containing P and Sn as the p-type semiconductor (3).

Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.

Abstract: Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the deuterium concentration near the interface to avoid subsequent depletion of deuterium due to diffusion. By using a rapid quench of a sintered wafer, the deuterium concentration near the interface is increased, because the rapid quench impedes the ability of the deuterium to diffuse away from the gate oxide interface.

Abstract: Novel semiconductor devices are monolithically defined with p-type and/or n-type wide bandgap material formed by impurity induced layer disordering of selected regions of multiple semiconductor layers. The devices are beneficially fabricated by simultaneously forming the n-type and/or p-type layer disordered regions with sufficiently abrupt transitions from disordered to ordered material. The novel devices include laterally and vertically oriented P-i-N or N-i-P photodetectors integrated with laterally oriented P-N-P or N-P-N bipolar transistors, respectively, an N-P-N or P-N-P bipolar transistor monolithically integrated with an edge emitting semiconductor laser, and laterally and vertically oriented P-i-N or N-i-P photodetectors integrated with the monolithically integrated bipolar transistor and edge emitting semiconductor laser.

Abstract: Method of producing a bromine compound having an aliphatic unsaturated bond which includes reacting a compound having an aliphatic unsaturated bond represented by the following general formula (1) with bromine:R.sup.1 --O--Ar.sup.1 --Y--Ar.sup.2 --O--R.sup.2 (1)to produce a bromine compound represented by the following formula (2):R.sup.3 --O--Ar.sup.1 --Y--Ar.sup.2 --O--R.sup.4 (2)wherein Ar.sup.1, Ar.sup.2 and Y are the same as defined in the above general formula (1) , and R.sup.3 and R.sup.4 are groups obtained by saturating the unsaturated groups of R.sup.1 and R.sup.2 in the above general formula (1) with bromine, respectively.The reaction is carried out in the presence of a solvent which is inactive in the reaction, and a substantial amount of the heat of reaction is removed from a reaction system by the vaporization of the solvent or bromine. A high-purity bromine compound in high yield which is useful as flame retardant, can be obtained.

Abstract: A semiconductor comprising an n-type semiconductor layer 1 with donor impurities added thereto, a semiconductor layer 2 having the value of energy from vacuum level to Fermi level larger than the value of energy from vacuum level to the lower end of the conduction band of the n-type semiconductor 1 and a junction connected to said semiconductor layer 2, characterized in that the donor impurities concentration (N.sub.d) in the range of thickness of the depletion layer generated in said n-type semiconductor layer 1 in contact with the junction boundary is at least2.7.times.10.sup.3 exp{-5.5(E.sub.C -E.sub.FS)}.times.N.sub.C(where E.sub.C is the energy value in eV from the upper end of the valence band to the lower end of the conduction band of the n-type semiconductor 1, E.sub.FS is the energy value in eV from the upper end of the valence band to the charge neutrality level of the n-type semiconductor 1, and N.sub.C is the effective density of states in cm.sup.

Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.

Abstract: A semiconductor device includes a buffer layer of AlGaAs that contains oxygen with a concentration level in the approximate range of 8.times.10.sup.17 cm.sup.-3 to 6.times.10.sup.19 cm.sup.-3, and carbon with a concentration level in the approximate range of 2.times.10.sup.16 cm.sup.-3 to 2.times.10.sup.17 cm.sup.-3. A lattice constant of the AlGaAs buffer layer is larger than a lattice constant of the GaAs substrate so a lattice misfit of the AlGaAs layer with respect to the GaAs substrate is equal to or varies by no more than 2.times.10.sup.5 from a corresponding lattice misfit between an undoped AlGaAs crystal with respect to the GaAs substrate. Oxygen atoms occupy an interstitial site, creating a deep impurity level that suppresses side gate effect.

Abstract: A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the molecules of the organic compound to release the group V element and oxygen.

Abstract: A semiconductor device for providing stable operation over a relatively wide temperature range includes a wide bandgap semiconductor active region having an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type which together produce a free carrier concentration at room temperature. The concentration of the intentional dopant in the active region is preferably less than 1.times.10.sup.16 cm.sup.-3 and the concentration of the unintentional impurity is less than 0.1 times the intentional dopant concentration so that the intentional dopant concentration will be less than 1000 times the free carrier concentration at room temperature. The intentional dopant concentration supplies substantially all the majority free carriers in the active region. The wide bandgap semiconductor active region is preferably diamond, IV-IV carbides, III-V nitrides and phosphides and II-VI selenides, tellurides, oxides and sulfides.

Abstract: Novel semiconductor devices are monolithically defined with p-type and n-type wide bandgap material formed by impurity induced layer disordering of selected regions of multiple semiconductor layers. The devices are beneficially fabricated by simultaneously forming the n-type and p-type layer disordered regions with sufficiently abrupt transitions from disordered to as-grown material. The novel devices include a heterojunction bipolar transistor monolithically integrated with an edge emitting heterostructure laser or a surface emitting laser, a heterostructure surface emitting laser, a heterostructure surface emitting laser having active distributed feedback, devices containing multiple buried layers which are individually contacted such as p-n junction surface emitting lasers, carrier channeling devices, and "n-i-p-i" or hetero "n-i-p-i" devices, and novel interdigitated structures, such as optical detectors and distributed feedback lasers.

Abstract: The invention relates to a semiconductor arrangement made of compound semiconductor material and consists in that the semiconductor body contains in areas and, in the case of phosphide compounds throughout its entirety or in areas, isoelectronic impurities made of an element whose covalent atom radius is larger than that of the element of the compound semiconductor, which the impurity material is isoelectronic.

Abstract: The disclosed improved GaAs majority carrier rectifying barrier diodes comprise a p.sup.+ region between semiconductor regions that comprise n-doped material. Exemplary structures are n.sup.+ -i-p.sup.+ -i-n.sup.+ and n.sup.+ -n-p.sup.+ -n-n.sup.+. The improvement comprises use of carbon as the p-dopant and results in readily manufacturable reliable devices.

Abstract: While depositing a III-V compound semiconductor layer from a vapor, carbon is added to group III and V elements to produce a p type conductivity region in the depositing semiconductor layer. Then, a small amount of n type dopant is added to the group III and V elements together with the carbon to produce an n type conductivity region in the depositing semiconductor layer. A sharp and precisely controlled doping profile is produced in the vicinity of a p-n junction, resulting in a semiconductor device having good initial performance and high reliability.

Abstract: A semiconductor structure with a p-type ZnSe layer has an improved ohmic contact consisting of a layer of Hg.sub.x Zn.sub.1-x Te.sub.a Se.sub.b Sc where x=0-1 with x being 0 at the surface of the ZnSe layer and increasing thereafter, a, b and c each =0-1 and a+b+c=1.

Abstract: The present invention comprises a semi-insulating layer of GaAs with p+ and layers of aluminum gallium arsenide AlGaAs grown on one side of the semi-insulating GaAs and with p and n+ layers of AlGaAs grown on the other side of the semi-insulating GaAs. Ohmic contacts are grown on both sides of the thyristor as well as low temperature GaAs to provide for surface passivity.

Abstract: An article of manufacture are disclosed comprising substantially increasing the electrical activation and mobility of electrons in a III-V semiconductor material containing minor amounts of oxygen by doping a III-V crystalline material with an n-type dopant and adding or implanting an oxygen reactive element in the III-V material where the doses of dopant and implanted oxygen reactive element are low enough to effect this increase. These doses typically do not exceed about 1E13 cm.sup.-2 and 4.5E12 cm.sup.-2 respectively. The added or implanted oxygen reactive element preferably is at a dose less than the n-type dopant. Experimental data indicate that the added or implanted oxygen reactive element acts as a gettering agent to form an oxygen depleted zone between dopant and oxygen reactive element regions.

Abstract: A device made by a process of making strain-free, heavily carbon-doped p-type epitaxial layers for use in high performance devices and at least one such device so made. The process essentially includes the epitaxial deposition of a strain-free, carbon-doped p-type layer in a GaAs HBT device to form the base layer thereof in a manner that includes the balancing of the strain of the crystal lattice structure caused by the carbon doping by co-doping the base layer with an isovalent and isoelectric dopant. The co-doping also improves device performance. It also effects alloy hardening, which inhibits further defect formation, improves mobility and carrier lifetime of the base layer and, by narrowing the energy gap, it improves ohmic contact formation.

Abstract: In a semiconductor device constituting a GaAs MESFET, a GaAs substrate is prepared from a base material containing boron ions as a dopant impurity having a total impurity concentration of 2.times.10.sup.17 atoms/cm.sup.3 or more. The boron ions are introduced into the GaAs substrate during crystal growth so that a uniform distribution of boron ions in the substrate results. Electrode layers are formed at predetermined portions on the GaAs substrate, and an active layer is formed to be adjacent to the electrode layers by ion implantation. Source and drain electrodes are formed on the electrode layers respectively, and a gate electrode is formed on the active layer.

Abstract: A lateral injection group III-V heterostructure device having self-aligned graded contact diffusion regions of opposite conductivity types and a method of fabricating such devices are disclosed. The device includes a heterojunction formed by a higher bandgap III-V compound semiconductor formed over a lower bandgap III-V compound semiconductor. The method of the present invention allows the opposite conductivity type diffusion regions to diffuse simultaneously and penetrate the heterojunction. This results in compositional mixing of the compound semiconductor materials forming the heterojunction in the diffusion regions.