With Specified Dopant (e.g., Plural Dopants Of Same Conductivity In Same Region) Patents (Class 257/607)
  • Patent number: 10271382
    Abstract: Embodiments disclosed herein relate to circular lamp arrays for use in a semiconductor processing chamber. Circular lamp arrays utilizing one or more torroidal lamps disposed in a reflective trough and arranged in a concentric circular pattern may provide for improved rapid thermal processing. The reflective troughs, which may house the torroidal lamps, may be disposed at various angles relative to a surface of a substrate being processed.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: April 23, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Joseph M. Ranish
  • Patent number: 10134724
    Abstract: An electro-static discharge (ESD) protection device includes a first PN diode, a second PN diode and a silicon controlled rectifier (SCR). The first PN diode and the second PN diode are coupled in series between a pad and a ground voltage to provide a first discharge current path. The SCR is coupled between the pad and the ground voltage to provide a second discharge current path. The SCR has a PNPN structure.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 20, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hyun Duck Lee
  • Patent number: 9972678
    Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 15, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • Patent number: 9905689
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; a fifth semiconductor region; an insulating portion that is provided between the second semiconductor region and the fifth semiconductor region and between the third semiconductor region and the fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; a second electrode; and a third electrode that is provided on the third semiconductor region and electrically connected to the third semiconductor region and the gate electrode.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Saito
  • Patent number: 9887160
    Abstract: A method of making an interconnect structure includes forming an opening within a dielectric material layer disposed on a substrate including a conductive material, the opening extending from a first surface to a second surface of the dielectric material layer and being in contact with a portion of the substrate; performing a plasma treatment process to chemically enrich exposed surfaces of the dielectric material that line the opening to form a chemically-enriched dielectric surface layer that included an element in a higher concentration than a remaining portion of the dielectric material layer; performing a chemical treatment process to remove a metal contact product from the portion of the substrate that is in contact with the opening; and disposing a conductive material in the opening to substantially fill the opening and form the interconnect structure.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terry A. Spooner, Wei Wang, Chih-chao Yang
  • Patent number: 9853104
    Abstract: A graphene compound made from the method of preparing graphene flakes or chemical vapor deposition grown graphene films on a SiO2/Si substrate; exposing the graphene flakes or the chemical vapor deposition grown graphene film to hydrogen plasma; performing hydrogenation of the graphene; wherein the hydrogenated graphene has a majority carrier type; creating a bandgap from the hydrogenation of the graphene; applying an electric field to the hydrogenated graphene; and tuning the bandgap.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 26, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Jeffrey W. Baldwin, Bernard R. Matis, James S. Burgess, Felipe Bulat-Jara, Adam L. Friedman, Brian H. Houston
  • Patent number: 9831182
    Abstract: A method of making an interconnect structure includes forming an opening within a dielectric material layer disposed on a substrate including a conductive material, the opening extending from a first surface to a second surface of the dielectric material layer and being in contact with a portion of the substrate; performing a plasma treatment process to chemically enrich exposed surfaces of the dielectric material that line the opening to form a chemically-enriched dielectric surface layer that included an element in a higher concentration than a remaining portion of the dielectric material layer; performing a chemical treatment process to remove a metal contact product from the portion of the substrate that is in contact with the opening; and disposing a conductive material in the opening to substantially fill the opening and form the interconnect structure.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: November 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 9793138
    Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 17, 2017
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventors: Deyuan Xiao, Richard R. Chang
  • Patent number: 9748151
    Abstract: The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 29, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Hiroshi Takeno
  • Patent number: 9702056
    Abstract: A region of an SiC solution in the vicinity of an SiC seed crystal is cooled while suppressing the temperature variation in a peripheral region of the SiC solution. An apparatus includes a seed shaft and a crucible for an SiC solution. The seed shaft has a lower end surface for attachment to an SiC seed crystal. The crucible comprises a main body, an intermediate cover, and a top cover. The main body includes a first cylindrical portion and a bottom portion at a lower end portion of the first cylindrical portion. The intermediate cover is within the first cylindrical portion and above the liquid level of the SiC solution in the main body. The intermediate cover has a first through hole for the seed shaft. The top cover is disposed above the intermediate cover and has a second through hole for the seed shaft to pass through.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 11, 2017
    Assignees: NIPPON STEEL & SUMITOMO METAL CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kazuhito Kamei, Kazuhiko Kusunoki, Nobuyoshi Yashiro, Nobuhiro Okada, Hironori Daikoku, Motohisa Kado, Hidemitsu Sakamoto
  • Patent number: 9680034
    Abstract: A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n? type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n? type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n? type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n? type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n? type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 13, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji Kitamura
  • Patent number: 9589804
    Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Shiu-Ko Jangjian, Chung-Ren Sun, Ming-Te Chen, Ting-Chun Wang, Jun-Jie Cheng
  • Patent number: 9558948
    Abstract: A semiconductor body having a first surface is provided. A deep doped region of the semiconductor body is formed using masked ion implantation to implant dopant atoms into a discrete region within the semiconductor body. A structured anti-reflective coating region is formed on a portion of the first surface that is aligned with the deep doped region in a lateral direction of the semiconductor body, the lateral direction being parallel to the first surface. A laser thermal anneal of the deep doped region of the semiconductor body is performed through the anti-reflective coating region thereby activating the implanted dopant atoms in the deep doped region.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Alexander Breymesser, Holger Schulze, Werner Schustereder
  • Patent number: 9543993
    Abstract: A radio frequency interconnect includes a plurality of transmitters. Each transmitter is associated with an individual carrier of a plurality of carriers. The radio frequency interconnect also includes a transmission channel communicatively coupled with the transmitters and a plurality of receivers communicatively coupled with the transmission channel. Each receiver is associated with a respective carrier. A combiner on a transmitter-side of the transmission channel is coupled with the transmitters between the transmitters and the transmission channel. A decoupler on a receiver-side of the transmission channel is coupled with the receivers between the receivers and the transmission channel. The radio frequency interconnect also includes at least one channel loss compensation circuit communicatively coupled between the plurality of transmitters and the plurality of receivers.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng Wei Kuo, Huan-Neng Chen, William Wu Shen
  • Patent number: 9496261
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: November 15, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachrin R. Sonkusale, Weimin Zhang
  • Patent number: 9450075
    Abstract: A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region. The undoped channel region, base dopant region, and threshold voltage setting region are disposed within the semiconductor substrate layer. The undoped channel region is disposed between the source electrode and the drain electrode, and the base dopant region and the threshold voltage setting region extend beneath the source electrode and the drain electrode. The threshold voltage setting region is disposed between the undoped channel region and the base dopant region.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 20, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Herb He Huang
  • Patent number: 9418850
    Abstract: A method includes forming an emitter at the first side of a semiconductor substrate by doping, wherein the dopant concentration is higher in the emitter than in the edge region; growing an oxide layer on the first side by annealing, wherein the oxide layer has a first thickness in a first region covering the emitter, and a second thickness in a second region covering the edge region. The first thickness is larger than the second thickness. Heavy metal ions are implanted through the first side with a first energy, and with a second energy, wherein the first energy and the second energy are different, such that the implanted heavy metal concentration in the edge region is higher than in the emitter due to an absorption of the oxide layer covering the emitter, resulting in a lower charge carrier lifetime in the edge region than in the emitter.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Oliver Humbel, Hans Millonig
  • Patent number: 9379208
    Abstract: A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 28, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Su-Hao Liu, Chien-Tai Chan, King-Yuen Wong, Chien-Chang Su
  • Patent number: 9337395
    Abstract: The present invention relates to production method and device applications of a new silicon (Si) semiconductor light source that emits at a single wavelength at 1320 nm with a full width at half maximum (FWHM) of less than 200 nm and a photoluminescence quantum efficiency of greater than 50% at room temperature. The semiconductor that is the base for the new light source includes a surface which is treated by an acid vapor involving heavy water or Deuterium Oxide (D2O) and a surface layer producing the light source at 1320 nm.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 10, 2016
    Assignee: TUBITAK
    Inventor: Seref Kalem
  • Patent number: 9331152
    Abstract: A semiconductor device includes: a gate oxide film formed on a surface of a semiconductor substrate; a gate electrode formed on the gate oxide film; and a high concentration impurity layer connected to a main electrode and formed on the surface of the semiconductor substrate, wherein an impurity species doped in the high concentration impurity layer comprises a first impurity species of phosphorous and a second impurity species of at least one of argon and nitrogen, a concentration of the second impurity species is higher than a concentration of the first impurity species in a surface of the high concentration impurity layer, and a peak position of a concentration distribution of the first impurity species in a depth direction in the high concentration impurity layer is deeper than a peak position of a concentration distribution of the second impurity species in the depth direction.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 3, 2016
    Assignee: Sanken Electric Co., LTD.
    Inventor: Toru Yoshie
  • Patent number: 9312130
    Abstract: A method of introducing a bandgap in single layer graphite on a SiO2 substrate comprising the steps of preparing graphene flakes and CVD grown graphene films on a SiO2/Si substrate and performing hydrogenation of the graphene. Additionally, controlling the majority carrier type via surface adsorbates.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 12, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Jeffrey W. Baldwin, Bernard R. Matis, James S. Burgess, Felipe Bulat-Jara, Adam L. Friedman, Brian H Houston
  • Patent number: 9208938
    Abstract: Various embodiments include inductor structures including at least one air gap for reducing capacitance between windings in the inductor structure. One embodiment includes an inductor structure having: a substrate; an insulation layer overlying the substrate; a conductive winding overlying the substrate within the insulation layer, the conductive winding wrapped around itself to form a plurality of turns substantially concentric about a central axis; an insulating structural support containing an air gap between the conductive winding and the insulation layer, the insulating structural support at least one of under, over or surrounding the plurality of turns of the conductive winding or between adjacent turns in the conductive winding; and at least one insulation pocket located radially inside a radially innermost turn in the plurality of turns with respect to the central axis.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, Anthony K. Stamper
  • Patent number: 9041157
    Abstract: An electrically actuated device comprises an active region disposed between a first electrode and a second electrode, a substantially nonrandom distribution of dopant initiators at an interface between the active region and the first electrode, and a substantially nonrandom distribution of dopants in a portion of the active region adjacent to the interface.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: May 26, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Sagi Varghese Mathai, Shih-Yuan (SY) Wang, Jianhua Yang
  • Publication number: 20150123248
    Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 7, 2015
    Applicant: SUNEDISON INC.
    Inventors: Robert J. Falster, Vladimir Voronkov
  • Publication number: 20150123247
    Abstract: A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 ?m along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×1017 cm?3 to 5×1017 cm?3 over the section L.
    Type: Application
    Filed: September 9, 2014
    Publication date: May 7, 2015
    Inventors: Thomas Neidhart, Franz Josef Niedernostheide, Hans-Joachim Schulze, Werner Schustereder, Alexander Susiti
  • Patent number: 9024414
    Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae Bum Kim
  • Publication number: 20150084162
    Abstract: An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 26, 2015
    Inventor: T. Jordan Davis
  • Publication number: 20150076660
    Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: TAI-I YANG, HONG-SENG SHUE, KUN-MING HUANG, CHIH-HENG SHEN, PO-TAO CHU
  • Patent number: 8981384
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Publication number: 20150069411
    Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Inventors: Romain Esteve, Jens Konrath, Daniel Kueck, David Laforet, Cedric Ouvrard, Roland Rupp, Andreas Voerckel, Wolfgang Werner
  • Patent number: 8975719
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
  • Patent number: 8969867
    Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10?5 ?·m or more and 4.8×10?3 ?·m or less.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yutaka Okazaki
  • Publication number: 20150054134
    Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 26, 2015
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Wataru ITO, Jun FUJISE
  • Patent number: 8946864
    Abstract: Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure. The film comprises a metal having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include metal ions that coalesce into a substantially continuous, electrically conductive metal layer, or that undergo covalent bonding, whereas in the absence of the embedded structure the metal ions instead may be free to diffuse through the substrate. The embedded structure may control the diffusion of the metal through the substrate and/or the reaction of the metal within the substrate.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: February 3, 2015
    Assignee: The Aerospace Corporation
    Inventors: Margaret H. Abraham, David P. Taylor
  • Publication number: 20150028453
    Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.
    Type: Application
    Filed: March 18, 2014
    Publication date: January 29, 2015
    Applicant: SK HYNIX INC.
    Inventor: Jae Bum KIM
  • Publication number: 20150014816
    Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.
    Type: Application
    Filed: December 30, 2013
    Publication date: January 15, 2015
    Applicant: ASM IP Holding B.V.
    Inventors: Keith Doran Weeks, John Tolle, Matthew G. Goodman, Sandeep Mehta
  • Patent number: 8927376
    Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Patent number: 8921979
    Abstract: A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Helmut Strack, Hans-Joerg Timme, Rainer Winkler
  • Publication number: 20140361408
    Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • Publication number: 20140361407
    Abstract: A method for forming a boron doped region within a silicon material substrate, and the resulting silicon material substrate that includes the boron doped region, each use a boron doped aluminum oxide material layer as a boron dopant source layer. The method provides the boron doped region with a sheet resistance in a range from about 15 to about 300 ohms per square. The method is also applicable, in general, to forming an n doped region, a p doped region or an n and p co-doped region within a silicon material substrate.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 11, 2014
    Applicants: SCHMID Group, University of Central Florida Research Foundation Inc.
    Inventors: Kristopher O. Davis, Winston V. Schoenfeld, Kaiyun Jiang, Dirk Habermann
  • Patent number: 8895417
    Abstract: A method and an apparatus for doping at least one of a graphene and a nanotube thin-film transistor field-effect transistor device to decrease contact resistance with a metal electrode. The method includes selectively applying a dopant to a metal contact region of at least one of a graphene and a nanotube field-effect transistor device to decrease the contact resistance of the field-effect transistor device.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski, Fengnian Xia
  • Patent number: 8890291
    Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 18, 2014
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Wataru Ito, Jun Fujise
  • Patent number: 8872307
    Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Siltronic AG
    Inventor: Katsuhiko Nakai
  • Patent number: 8858843
    Abstract: A high-fidelity dopant paste is disclosed. The high-fidelity dopant paste includes a solvent, a set of non-glass matrix particles dispersed into the solvent, and a dopant.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 14, 2014
    Assignee: Innovalight, Inc.
    Inventors: Elena Rogojina, Maxim Kelman, Giuseppe Scardera
  • Patent number: 8853438
    Abstract: Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant may include arsenic (As). In an embodiment, a dopant solution is provided that includes a solvent and a dopant. In a particular embodiment, the dopant solution may have a flashpoint that is at least approximately equal to a minimum temperature capable of causing atoms at a surface of the substrate to attach to an arsenic-containing compound of the dopant solution. In one embodiment, a number of silicon atoms at a surface of the substrate are covalently bonded to the arsenic-containing compound.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Dynaloy, LLC
    Inventors: Spencer Erich Hochstetler, Kimberly Dona Pollard, Leslie Shane Moody, Peter Borden Mackenzie, Junjia Liu
  • Publication number: 20140291809
    Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventors: Hans-Joachim Schulze, Frank Pfirsch, Hans-Joerg Timme
  • Publication number: 20140284768
    Abstract: A semiconductor structure comprising a first semiconductor layer, a bulk semiconductor layer, an insulation layer between the first semiconductor layer and the bulk semiconductor layer, a first implanted region that is at least partially within the insulation layer; and a second doped region that is at least partially within the bulk semiconductor layer, wherein the first implanted region has an implant profile that shows a maximum within the insulation layer and a tail extending within the bulk semiconductor layer so as to inhibit the diffusion of a second doping material of the second doped region within the insulation layer.
    Type: Application
    Filed: November 13, 2012
    Publication date: September 25, 2014
    Applicant: SOITEC
    Inventor: Konstantin Bourdelle
  • Publication number: 20140264754
    Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Shyam Surthi
  • Publication number: 20140252553
    Abstract: In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures.
    Type: Application
    Filed: February 3, 2014
    Publication date: September 11, 2014
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Zhongping Liao
  • Publication number: 20140252554
    Abstract: In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator.
    Type: Application
    Filed: February 3, 2014
    Publication date: September 11, 2014
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Zhongping Liao