Abstract: A device comprising a semiconductor substrate, an electrically-conductive layer covering the substrate, and an insulating sheath, the conductive layer being in contact with the insulating sheath on the side opposite to the substrate.

Abstract: This invention includes multiple quantum well and quantum dot channel FETs, which can process multi-state/multi-bit logic, and multibit-bit inverters configured as static random-access memories (SRAMs). SRAMs can be implemented as flip-flops and registers. In addition, multiple quantum well and quantum dot channel structures are configured to function as multi-bit high-speed quantum dot (QD) random access memories (NVRAMs). Multi-bit Logic, SRAMs and QD-NVRAMs are spatially located on a chip, depending on the application, to provide a low-power consumption and high-speed hardware platform. The multi-bit logic, SRAM and register, and QD-NVRAM are implemented on a single chip in a CMOS-like platform for applications including artificial intelligence (AI) and machine learning.

Abstract: A semiconductor package includes a core layer formed of a ferromagnetic material, and includes a frame passing through the core layer and having a through-hole, a semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed, and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of the semiconductor chip, and a first connection structure including a first redistribution layer disposed on the active surface of the semiconductor chip and electrically connected to the connection pad.

Abstract: A chip package may include a first polymer layer and a first semiconductor chip in the first polymer layer. The first semiconductor chip may include a first semiconductor device and a first semiconductor substrate supporting the first semiconductor device. The first semiconductor chip may also have a first contact pad coupled to the first semiconductor device. The first semiconductor chip may further include a first conductive interconnect on the first contact pad. The chip package may also include a second polymer layer on the first polymer layer and across an edge of the first semiconductor chip. The chip package may further include a first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and across the edge of the first semiconductor chip.

Abstract: A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die.

Abstract: A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; coating a monolayer containing fluorine on the interfacial layer; and forming a gate layer on the interfacial layer.

Abstract: A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively.

Abstract: A light emitting package includes a circuit board, a light emitting chip disposed on the circuit board and electrically connected to the circuit board, a resin layer disposed on the light emitting chip, and a fluorescent layer disposed on the resin layer. The light emitting chip is disposed between the resin layer and the circuit board. The resin layer is disposed between the light emitting chip and the fluorescent layer. For a light, a refractive index of the resin layer is smaller than a refractive index of the light emitting chip and is larger than a refractive of the fluorescent layer.

Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.

Abstract: In a method for producing a semiconductor body, impurities which act as recombination centers in the semiconductor body and form a recombination zone are introduced into the semiconductor body during the process of producing the semiconductor body. In a semiconductor component, comprising a semiconductor body having a front surface and an opposite rear surface, and also a recombination zone formed by impurities between the front and rear surfaces, wherein the impurities act as recombination centers, the surface state density at the front and rear surfaces of the semiconductor body is just as high as the surface state density at a front and rear surface of an identical semiconductor body without a recombination zone.

Abstract: A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.

Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.

Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.

Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material.

Abstract: Provided are a semiconductor device which can shorten reverse recovery time without increasing leakage current between the drain and the source, and a fabrication method for such semiconductor device.

Abstract: Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

Abstract: The invention provides a technique and a device that dramatically improve joint reliability of miniature joints of fine electronic components. According to the invention, when producing a tin or a solder alloy used for electronic components, an ingot of a tin or a solder alloy is heated, melted and delivered to a reactor. Also, a solution containing organic acid having a carboxyl group (—COOH) is delivered to the reactor. After stirring and mixing the two liquids intensively, the mixed liquid is separated into a molten tin or a molten solder alloy liquid and an organic acid solution according to the difference in specific gravity. Then, the respective liquids are circulated to the reactor, and the metal oxides and the impurities existing in the molten tin or the molten solder alloy are removed, and the molten tin or the molten alloy is purified to have oxygen concentration of 5 ppm or less.

Abstract: An integrated circuit mount system includes an integrated circuit, a solder mask for the integrated circuit, and a solder mask pad on the substrate with the solder mask.

Abstract: A low noise transistor and a method of making a low noise transistor. A noise-reducing agent is introduced into the gate electrode and then moved into the gate dielectric of a transistor.

Abstract: The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.

Abstract: The invention relates to a semiconductor component comprising a buried temporarily n-doped area (9), which is effective only in the event of turn-off from the conducting to the blocking state of the semiconductor component and prevents chopping of the tail current in order thus to improve the turn-off softness. Said temporarily effective area is created by implantation of K centers (10).

Abstract: A solid-state optical device includes a solid-state element, a power supplying/retrieving portion on which the solid-state element is mounted, the power supplying/retrieving portion supplying or retrieving electric power to/from the solid-state element, and a glass sealing material that seals the solid-state element. The glass sealing material has a thermal expansion coefficient equivalent to that of the power supplying/retrieving portion. The glass sealing material includes a P2O5—Al2O3—ZnO-based low-melting glass that includes 55 to 62 wt % of P2O5, 5 to 12 wt % of Al2O3 and 20 to 40 wt % of ZnO in weight %.

Abstract: A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located under the N-type doped regions and the P-type doped regions and fully isolates the N-type doped regions from the N-well.

Abstract: The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.

Abstract: A solid-state optical device having: a solid-state element; a power supplying/retrieving portion that supplies or retrieves electric power to/from the solid-state element; and a glass sealing material that seals the solid-state element. The glass sealing material is made of a P2O5—ZnO-based low-melting glass that has 45 to 50 wt % of P2O5 and 15 to 35 wt % of ZnO.

Abstract: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and the carrier supply layer or depleted, the carrier supply layer has a band gap energy greater than that of the channel layer, and x in the formula AlxGa1-xN decreases monotonically with an increase in the distance from the interface. The channel layer may be crystalline of gallium nitride. The channel layer may be undoped. X of the formula AlxGa1-xN of the carrier supply layer is greater than or equal to 0.15 and less than or equal to 0.40 at the interface.

Abstract: A semiconductor device has an n?-semiconductor layer and p+-diffusion regions each having a depth of 14 to 20 ?m (design value) selectively formed in the n? semiconductor layer. With the entire surface of the chip irradiated with light ions, such as He ions, a lifetime killer is introduced from a position d2 shallower than a position d1 of a p-n junction surface, formed from the n?-semiconductor layer and the p+-diffusion regions, to a position d3 deeper than the position d1 to form a short-lifetime region over the entire chip. The irradiation is carried out so that the light ion irradiation half width is not more than the depth of the p+-diffusion regions and a position of a peak of the light ions becomes deeper than the light ion irradiation half width and within the range between 80% and 120% of the depth of the p+-diffusion regions.

Abstract: A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well region provided in the support substrate under the MOSFET.

Abstract: An electronic power device comprising a single crystal silicon segment being characterized in that the segment comprises a non-uniform distribution of minority carrier recombination centers, the minority carrier recombination centers comprising a substitutional metal, with the concentration of the centers in a bulk layer being greater than the concentration in a surface layer. The centers have a concentration profile in which the peak density of the centers is at or near the central plane with the concentration generally decreasing from the position of peak density in the direction of the front surface of the segment and generally decreasing from the position of peak density in the direction of the back surface of the segment.

Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

Abstract: The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.

Abstract: A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region formed beside the gate electrode, wherein the source/drain region 4 comprises a first impurity diffusion region including a first P-type impurity and located in the proximity of a surface of the semiconductor substrate, and a second P-type impurity diffusion region located below the first impurity diffusion region and including a second P-type impurity having a smaller diffusion coefficient in the semiconductor substrate than the first P-type impurity.

Abstract: A semi-conductor light emitting diode includes closely spaced n and p electrodes formed on the same side of a substrate to form an LED with a small foot-print. A semi-transparent U shaped p contact layer is formed along three sides of the top surface of the underlying window layer. The p electrode is formed on the p contact layer centered on the closed end of the U shaped layer. An n contact layer is formed on an n cladding layer and centered in the open end of the U of the p contact layer. The n electrode is formed on the n contact layer. The n and p electrodes are electrically isolated from one another by either a trench or an insulator, situated between the electrodes.

Abstract: A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime region, in which the carrier lifetime is short, formed in such a configuration that the first carrier lifetime region extends across the edge area of an anode electrode projection, which projects the anode electrode vertically into a semiconductor substrate. The first carrier lifetime region also includes a vertical boundary area spreading nearly vertically between a heavily doped p-type anode layer and a lightly doped semiconductor layer. The first carrier lifetime region of the invention is formed by irradiating with a particle beam, such as a He2+ ion beam or a proton beam.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.

Abstract: A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer of transistors is formed onto the film. The second substrate is removed at a temperature within a low temperature range. The semiconductor film is bonded with the first layer of transistors onto a second layer of transistors of a third substrate.

Abstract: An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1×1014 to 5×1015 cm−2. Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 &mgr;m or less.

Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.