Abstract: The present invention provides, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region that are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by impurities, such as inert-gas, metals, Group III elements, Group IV elements and Group V elements, introduced to a predetermined region in this channel region, or by defects generated due to the introduction of these impurities. The present invention thus provides an arrangement restraining bipolar transistor type behavior to stabilize saturation current and to provide a TFT that can improve reliability.

Abstract: A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first trench-type gate electrode formed on the first gate insulation film and arranged in parallel and extending through the first semiconductor region in a direction of depth thereof.

Abstract: A technique of improving a reverse recovery characteristic of a semiconductor device which solves a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover. To solve the technical problem, in a PN junction between a P type layer and an N type layer, a heavy metal such as platinum is firstly diffused into an—layer and N+ layer of the N type layer. Subsequently, helium ion is implanted into the inside of the—layer from the interface between the P type layer and the N+ layer to a predetermined depth, so that the N− layer in the vicinity of the junction is damaged to form, in the—layer, a low lifetime region having a carrier lifetime smaller than that of the N type layer and a resistibility that decreases monotonically. Such a technique may be applied to diodes, and particularly, free-wheel diodes in power modules.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) with

Abstract: The present invention includes polishing the wafer backside by a grinder. Subsequently, a glass is laminated on the wafer backside surface by using epoxy. Then, the wafer is etched to isolate the dies. An epoxy is then coated on the wafer by means of vacuum coating process. Then, a curing step is performed by using the ultraviolet (UV) radiation to harden the epoxy. A grinding process is optional used to grind the epoxy on the wafer circuit side. A plurality of pad openings is formed in the epoxy. Subsequently, a pad circuit re-distribution is arranged over the upper surface of the epoxy. A solder mask covers the epoxy and the pad circuit for isolation. A printing process is carried out to print solder on the pre-determined area and the solder contacts to the pad circuit. Then, the solder is re-flow, and the wafer is then set to a testing apparatus for wafer level testing.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

Abstract: Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a “pinched off” gate region when no bias is applied to the gate. In particular embodiments of the present invention, the semiconductor devices include a silicon carbide drift layer of a first conductivity type, the silicon carbide drift layer having a first face and having a channel region therein. A buried base region of a second conductivity type semiconductor material is provided in the silicon carbide drift layer so as to define the channel region. A gate layer of a second conductivity type semiconductor material is formed on the first face of the silicon carbide drift layer adjacent the channel region of the silicon carbide drift layer. A gate contact may also be formed on the gate layer. Both transistors and thyristors may be provided.

Abstract: A nitride-type III-V group compound semiconductor device includes a substrate and a layered structure including at least a channel layer using two-dimensional electron gas formed over a substrate, wherein the channel layer contains InN.

Abstract: A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such that the carbon atoms absorb point defects created in the substrate during device fabrication but do not adversely affect the leakage characteristics of the device.

Abstract: Power semiconductor devices include a semiconductor substrate having a face thereon and a buried electrically insulating layer extending laterally in the semiconductor substrate and having an opening therein. A drift region of first conductivity type is also provided in the semiconductor substrate. To improve breakdown voltage characteristics, the drift region extends through the opening in the buried electrically insulating layer and has a first conductivity type doping concentration therein that is established at a level sufficient to generate a first conductivity type charge density of between 1.times.10.sup.12 cm.sup.-2 and 5.times.10.sup.13 cm.sup.-2 across the opening.

Abstract: Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the deuterium concentration near the interface to avoid subsequent depletion of deuterium due to diffusion. By using a rapid quench of a sintered wafer, the deuterium concentration near the interface is increased, because the rapid quench impedes the ability of the deuterium to diffuse away from the gate oxide interface.

Abstract: A method for improving the operating stability of compound semiconductor minority carrier devices and the devices created using this method are described. The method describes intentional introduction of impurities into the layers adjacent to the active region, which impurities act as a barrier to the degradation process, particularly undesired defect formation and propagation. A preferred embodiment of the present invention uses O doping of III-V optoelectronic devices during an epitaxial growth process to improve the operating reliability of the devices.

Abstract: A semiconductor device on a semiconductor wafer, wherein improvements are realized to agglomeration control, resistivity, and thermal stability of a titanium disilicide layer on a polysilicon layer. Agglomeration control is achieved through the use of two carefully selected low dose barrier diffusion matrix implants into the polysilicon layer, one of which is situated at an interface between the layer of polysilicon and the resultant layer of titanium disilicide film after heat treatment, and the other of which is near the surface of the resultant layer of titanium disilicide film after heat treatment.

Abstract: A compound semiconductor integrated circuit having a high resistance layer consisting of a compound semiconductor to which oxygen is added as an impurity and an undoped compound semiconductor layer which are formed between a semi-insulating substrate and field effect transistors formed thereon sequentially from the semi-insulating substrate side is suited to a superspeed operation because the low frequency oscillation is suppressed.

Abstract: An N.sup.- layer (11) of a low impurity concentration is formed on an upper major surface of an N.sup.+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N.sup.- layer (11) is in a multilayer structure of first to third regions (11a to 11c) having carrier lifetimes .tau..sub.1, .tau..sub.2 and .tau..sub.3 respectively. These lifetimes are in relation .tau..sub.2 <.tau..sub.1 <.tau..sub.3. Due to the large lifetime .tau..sub.3 of the third region (11c), soft recovery can be implemented. The fact that the lifetime .tau..sub.3 of the third region (11c) is large serves as a factor reducing a forward voltage V.sub.f. It is possible to attain soft recovery without increasing the forward voltage V.sub.F by properly designing these lifetimes and thicknesses.

Abstract: A semiconductor fabrication method improves the voltage characteristic of floating-body MOSFETs by creating recombination centers near the source-body junction of the device. A MOSFET is fabricated through the passivation oxidation stage, and a photolithography step is used to expose the source region. Implantation is then performed using one of two types of material. A first type creates electron traps of predetermined energy in the vicinity of the source-body junction. A second type creates defects in the crystalline structure of the semiconductor material. Both implantation types create recombination centers in the material. This allows the discharge through the source-body junction of charges built up in the body region.

Abstract: A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the molecules of the organic compound to release the group V element and oxygen.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: Reactor atoms (22) are introduced into a silicon substrate (10) by ion implantation to combine with metal impurities (18) to form stable chemical compounds (24). The stable compounds do not decompose and release the metal impurities during subsequent processing steps. Such metal impurities are detrimental to semiconductor devices formed in active regions (16, 17) in the silicon substrate. The reactor atoms such as sulfur are chosen to be substantially immobile in silicon at normal semiconductor processing temperatures. The metal impurities such as iron are effectively gettered to increase performance and reliability of semiconductor devices formed in the active regions (16, 17) in the silicon substrate.

Abstract: A principal feature of the present invention is to obtain a semiconductor device including a silicon thin film for use as interconnections or an electrode. The semiconductor device includes a semiconductor substrate, and a silicon thin film provided on the semiconductor substrate. Arsenic and carbon are added in the silicon thin film. The arsenic is distributed at a uniform concentration along a depth of the silicon thin film.

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract: A microelectronic device of the MOSFET type (20) is structured to exhibit low noise characteristics at cryogenic temperatures of less than about 40K. The device (20) comprises a doped silicon substrate wafer (22), the dopant having an ionization energy in the substrate of more than about 0.1 eV. Preferred substrate dopants include tellurium as an n-type dopant and indium as a p-type dopant. A metal-oxide-semiconductor field effect transistor (20) in the substrate wafer (22) includes a source (24), a drain ( 26 ), and a gate (30) intermediate the source (24) and the drain (26).

Abstract: A semiconductor substrate allowing prevention of the breakdown voltage degradation of a gate oxide film and having a prescribed mechanical strength in order to cope with increase in the diameters of wafers corresponding to reduction in the dimensions of semiconductor devices and improvement in productivity, and a Bi-CMOS semiconductor device allowing electrical characteristics to be maintained in any of a bipolar transistor and a field effect transistor are provided. An epitaxial layer is formed on a silicon wafer formed by means of CZ method. A silicon wafer formed by means of FZ method is joined onto the epitaxial layer. An npn bipolar transistor is formed in the epitaxial layer. An n channel MOS transistor and a p channel MOS transistor are formed in the silicon wafer.

Abstract: A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Abstract: An article of manufacture are disclosed comprising substantially increasing the electrical activation and mobility of electrons in a III-V semiconductor material containing minor amounts of oxygen by doping a III-V crystalline material with an n-type dopant and adding or implanting an oxygen reactive element in the III-V material where the doses of dopant and implanted oxygen reactive element are low enough to effect this increase. These doses typically do not exceed about 1E13 cm.sup.-2 and 4.5E12 cm.sup.-2 respectively. The added or implanted oxygen reactive element preferably is at a dose less than the n-type dopant. Experimental data indicate that the added or implanted oxygen reactive element acts as a gettering agent to form an oxygen depleted zone between dopant and oxygen reactive element regions.

Abstract: In a photothyristor, a main thyristor consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed on a semiconductor substrate. Also a pilot thyristor surrounded with the main thyristor and consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed. In the P gate base layer, a trigger light irradiation surface including the inner surface of a recess is formed on the center of the pilot thyristor. In the N base layer, a crystal defect layer is formed under the trigger light irradiation surface by the irradiation with a radiant ray. A breakdown voltage to protect the thyristor from overvoltage is controlled by the crystal defect layer.

Abstract: In a semiconductor device constituting a GaAs MESFET, a GaAs substrate is prepared from a base material containing boron ions as a dopant impurity having a total impurity concentration of 2.times.10.sup.17 atoms/cm.sup.3 or more. The boron ions are introduced into the GaAs substrate during crystal growth so that a uniform distribution of boron ions in the substrate results. Electrode layers are formed at predetermined portions on the GaAs substrate, and an active layer is formed to be adjacent to the electrode layers by ion implantation. Source and drain electrodes are formed on the electrode layers respectively, and a gate electrode is formed on the active layer.