Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si--Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: A semiconductor photodetector having a planar structure, including a first silicon layer having a first conductivity and formed with a recess, a silicon dioxide film covering a sidewall of the recess therewith, a germanium monocrystal layer formed in the recess, a first germanium layer having a first conductivity and sandwiched between the germanium monocrystal layer and the first silicon layer in the recess, a second germanium layer having a second conductivity and formed on the germanium monocrystal layer, and a second silicon layer having a second conductivity and formed on the second germanium layer. The first and second germanium layers prevent a depletion layer, which are generated in the germanium monocrystal layer when a voltage is applied to the semiconductor photodetector, from reaching the first and second silicon layers, respectively.

Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.

Abstract: The boundary between the P type silicon base and N.sup.+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: An anti-reflective composition used in manufacturing integrated circuit devices comprises a silicon-added germanium nitride material. The composition is present in a solid solution.

Abstract: A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium.

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: A semiconductor device which does not allow production of leak current or a drop of the Early voltage and includes a diffused layer having a reduced depth. A silicon layer containing an impurity of a second conduction type is formed on a semiconductor substrate of a first conduction type, and a spacer layer formed from a single crystalline silicon layer containing germanium is provided under the silicon layer.

Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.

Abstract: A Germanium junction field effect transistor (Ge-JFET) is fabricated in a manner to produce low noise and which is particularly suitable for a cryogenic detector. The Ge-JFET in accordance with the present invention comprises a germanium base material on which a phosphorous implanted channel region is implanted thereon. A boron cap layer overlies the channel region. On the cap layer are separately spaced drain and source ohmic contact regions, and a gate ohmic contact region therebetween. The drain and source ohmic contact regions are separately spaced arsenic implant regions and a phosphorous implant region. The gate ohmic contact region is a BF.sub.2 implanted region.

Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.

Abstract: A semiconductor window which is transparent to light in the infrared range and which has good electrical conductivity is formed of a prefabricated semiconductor sheet bonded to a substrate material by optical contact. The sheet is a substantially uniformly doped wafer sufficiently thin that inherent absorption bands do not affect transmission. The sheet is contact bonded to the surface of an undoped transparent substrate without diffusion, growth or deposition on the surface. Windows having particular optical band pass characteristics are formed utilizing a zinc selenide substrate and a gallium arsenide sheet.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.

Abstract: A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transconductance of the device can be optimized by controlling the location of the carriers within the channel.

Abstract: A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon oxide surfaces; and the resulting product of such a process. The polycrystalline silicon is selectively deposited over the single crystal silicon substrate by first forming a thin layer of a lattice mismatched material over the single crystal silicon surface, and then depositing a layer of polycrystalline silicon over the lattice mismatched material. Preferably, the thin lattice mismatched layer comprises a silicon/germanium (SiGe) alloy.

Abstract: A photodetection semiconductor device is constructed in such a manner that a photodiode light absorbing layer includes an Si/SiGe super-lattice layer (6), which forms a layer in parallel with the surface of a silicon substrate (1), and upper and lower P type low Ge concentration SiGe epitaxial layers (5) and (7), which sandwich the Si/SiGe super-lattice layer between them and contain Ge lower than a Ge content in the Si/SiGe super-lattice layer, a highly dense P+ type Si contact layer (8) is directly formed on the upper SiGe epitaxial layer (7) and a highly dense N+ type epitaxial layer (2) is formed immediately below the lower SiGe epitaxial layer (5). Preferably, Ge concentration in each of the upper and lower SiGe epitaxial layers (5) and (7) is set to be at least 1% or higher.

Abstract: A base region structure of a bipolar transistor is provided. The base region structure is formed over both an epitaxial layer having a first conductivity type and an insulation film. The base region structure comprises a single layer having a first conductivity type. The single layer comprises both an epitaxial portion extending over the epitaxial layer and a polycrystal portion extending over the insulation film. An emitter region is formed at an upper part of the epitaxial portion. The epitaxial portion serves as a base region and the polycrystal portion serves as a base plug lead.

Abstract: A germanium-based field effect transistor has a passivation layer of aluminum oxide below a germanium channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurities, particularly arsenic released in the oxide layer as a result of forming the oxide layer. The low surface state germanium channel has very low phase noise and is suitable for use as a local oscillator in a heterodyne receiver.

Abstract: A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transconductance of the device can be optimized by controlling the location of the carriers within the channel.

Abstract: A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silicon oxide layer serving as a gate insulation layer is formed on the channel region. A gate terminal is formed on the second silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.

Abstract: A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed.

Abstract: An SOI transistor whose source region and/or drain region have a heterostructure made up of at least two different semiconductor materials, to thereby prevent a bipolar-induced breakdown.

Abstract: A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.

Abstract: A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the toughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed.

Abstract: A power device structure which is formed of two merged device structures: an FET control device is located in a surface layer of narrower-bandgap material, and a blocking device which provides high-voltage-withstand capability is located deeper in the device, in a substrate of wider-bandgap material.

Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material utilizing an approximately one monolayer thick monovalent surfactant element.

Abstract: This invention relates to a semiconductor device comprising at least one p-n junction. The junction is formed from a "p" semiconductor contacting an "n" semiconductor. Said device characterized in that at least one of said "p" or "n" semiconductor is a nanoporous crystalline semiconducting material. These nanoporous materials have an intracrystalline nanopore system whose pores are crystallographically regular and have an average pore diameter of about 2.5 to about 30 .ANG.. Additionally, they have a band gap of greater than 0 to about 5 eV which band gap can be modified by removing a portion of the templating agent from the pore system of the materials. The materials which have these properties include, metal polychalcogenide compounds, metal sulfides and selenides, metal oxides, and metal oxysulfides. These materials can be used in a large variety of semiconducting devices such as light emitting diodes, bipolar transistors, etc. A process for preparing these nanoporous materials is also presented.

Abstract: A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the device capacitances are reduced, and the transistor can be combined with fully-depleted CMOS in a SOI-BiCMOS technology.

Abstract: A thermoelectric element having a very large number of alternating layers of semiconductor material. The alternating layers all have the same crystalline structure. The inventors have demonstrated that materials produced in accordance with this invention provide figures of merit more than six times that of prior art thermoelectric materials. A preferred embodiment is a superlattice of Si, as a barrier material, and SiGe, as a conducting material, both of which have the same cubic structure. Another preferred embodiment is a superlattice of B--C alloys, the layers of which would be different stoichiometric forms of B--C but in all cases the crystalline structure would be alpha 0. In a preferred embodiment the layers are grown under conditions as to cause them to be strained at their operating temperature range in order to improve the thermoelectric properties.

Abstract: Silicon-based laser diodes, optical amplifiers, electrooptical modulators, and photodetectors in which the active region consists of a pseudomorphic GeSn multiple quantum well stack. Each quantum well is tensile-strained Ge.sub.1-x Sn.sub.x layer sandwiched between compressively strained barriers of Ge.sub.1-y Sn.sub.y with x.about.0.1, x<y and y.about.0.15. The GeSn quantum wells have a strain-induced direct gap for strongly allowed band-to-band transitions in the infrared range. The quantum well stack is grown upon a relaxed SiGeSn alloy buffer portion whose composition is graded up from a lattice match at the silicon substrate interface to a Ge or GeSn composition at buffer's top surface. Doped cladding layers are added, so that the devices have a p-i-n diode structure. The monolithic integrated Column IV devices have a rib waveguide structure, where desired, and operate typically in the 2 to 3 micron wavelength range.

Abstract: A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.

Abstract: A BiCMOS semiconductor device includes a pair of p-channel and n-channel MOS field effect transistors, a hetero-junction bipolar transistor including an epitaxial base layer made of a first compound semiconductor, and a homo-junction bipolar transistor including a base layer made of a second semiconductor. The hetero-junction bipolar transistor is operated in a low collector current region less than a critical collector current value at which the hetero-junction bipolar transistor has the maximum value of a cutoff frequency thereof. The homo-junction bipolar transistor is operated in a high collector current region more than a critical collector current value at which the homo-junction bipolar transistor has the maximum value of a cutoff frequency thereof.

Abstract: A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract: An MIS transistor has a channel portion of a first conduction type of first semiconductor material formed on an insulating substrate, second conduction type source and drain regions sandwiching said channel portion therebetween, and a gate electrode formed on a main surface of the channel portion with an insulating film therebetween, wherein the source region is made of the first semiconductor material and a second semiconductor material having an energy band gap smaller than that of the first semiconductor material and a heterojunction between the first and second semiconductor materials is provided outside of a depletion layer region formed in the junction between the source and channel portions, and inside a diffusion length L.sub.d from a depletion edge.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.

Abstract: A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Abstract: A semiconductor device with HBT that enables the cutoff frequency of the HBT to be restrained from lowering at higher collector current levels. The HBT has an emitter region, a SiGe base region, and first and second SiGe collector regions. The first collector region is adjacent to the base region. The base region has a first distribution of Ge concentration graded as a function of depth. The Ge concentration of the first distribution increases at a first gradient as a function of depth from a base-emitter junction to a base-collector junction. The first and second collector regions have second and third distributions of Ge concentration graded as a function of depth. A minimum Ge concentration of the second distribution is not lower than a maximum Ge concentration of the third distribution.

Abstract: A multi-layer superlattice quantum well thermoelectric material using materials for the layers having the same crystalline structure. A preferred embodiment is a superlattice of Si and SiGe, both of which have a cubic structure. Another preferred embodiment is a superlattice of B-C alloys, the layers of which would be different stoichometric forms of B-C but in all cases the crystalline structure would be alpha rhombohedral.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract: A Metal Insulator Semiconductor (MIS) heterojunction transistor. The MIS transistor is in a layered wafer having a n.sup.+ Si substrate, n Si collector layer, and a p Si/SiGe base. The base Si/SiGe interface may be vertical or horizontal. A thin oxide layer separates the base from the emitter, which is of a low work function metal such as Al, Mg, Mn, or Ti.

Abstract: Disclosed is a semiconductor device such as a light emitting diode, a MOS transistor, a Schottky diode, and CCD. The semiconductor device comprises a SiC layer of a first conductivity type and another SiC layer of a second conductivity type. At least one of the SiC layers of the first and second conductivity types is doped with at least one element selected from the group consisting of Cr, Mo and W.

Abstract: A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon.

Abstract: Holes generated by impact ionization in a SOI-MOS transistor is removed from the channel region to improve the breakdown voltage between the source and drain. A channel region of the SOI-MOS transistor is formed of a p type silicon layer. A drain region is formed of an n type silicon layer. A source region adjacent to the channel region includes an n type germanium layer. The forbidden energy band gap width of the germanium is smaller than that of the silicon. The n type germanium layer is formed in at least a portion of the source region. This layer is formed by ion-implanting germanium into a portion of the silicon layer, or removing a portion of the silicon layer, followed by growing a germanium layer in an epitaxial manner thereabove.

Abstract: There is interposed a buffer film composed of IIa group fluoride and having characteristics of orientation to a surface direction (111), in which mismatching in lattice constant with a crystal element of a semiconductor substrate is large and mismatching in lattice constant with IV-VI group compound ferroelectric substance is small, between the semiconductor substrate having a surface direction (100) and a ferroelectric gate film comprising the IV-VI group compound ferroelectric substance and having characteristics of polarization to the surface direction (111). Since the buffer film is an orientation film in the direction of (111) without influenced by a crystal element of the semiconductor substrate serving as a base material, the ferroelectric gate film can be oriented in the direction of (111) which is the same as the direction of polarization of the ferroelectric substance.

Abstract: A heterojunction type of compound semiconductor integrated circuit in which a PNP transistor has an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor, a P type second compound semiconductor limitedly arranged on a part of the substrate for functioning as an emitter of the PNP transistor, an N type third compound semiconductor arranged on both the second compound semiconductor and the substrate for functioning as a base of the PNP transistor, electrons being applied from the substrate to the third compound semiconductor, a P type fourth compound semiconductor limitedly arranged on a part of the N type third compound semiconductor, a P.sup.