Abstract: A Schottky barrier diode includes a semiconductor layer including a Ga2O3-based single crystal, an anode electrode that forms a Schottky junction with the semiconductor layer and is configured so that a portion in contact with the semiconductor layer includes Mo or W, and a cathode electrode. A turn-on voltage thereof is not less than 0.3 V and not more than 0.5 V.

Abstract: Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

Abstract: A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.

Abstract: An object of the present invention is to provide a Schottky barrier diode using gallium oxide capable of suppressing heat generation and enhancing heat radiation performance while ensuring mechanical strength and handling performance. A Schottky barrier diode includes a semiconductor substrate 20 made of gallium oxide having a recessed part 23 on the second surface 22, an epitaxial layer 30 made of gallium oxide and provided on a first surface 21 of the semiconductor substrate 20; an anode electrode 40 provided at a position overlapping the recessed part 23 as viewed in the lamination direction and brought into Schottky contact with the epitaxial layer 30, and a cathode electrode 50 provided in the recessed part 23 of the semiconductor substrate 20 and brought into ohmic contact with the semiconductor substrate 20.

Abstract: Disclosed herein is a multilayer nanocrystal structure comprising a nanocrystal alloy core comprising two or more nanocrystals and including an alloy interlayer formed at an interface between the two or more nanocrystals, and one or more layers of nanocrystal shells formed sequentially on the surface of the nanocrystal alloy core, wherein the nanocrystal shells each have different band gaps. The multilayer nanocrystal structure can be applied to various electronic devices owing to its advantages of high luminescence efficiency, superior optical stability, and superior chemical stability.

Abstract: In various embodiments, controlled heating and/or cooling conditions are utilized during the fabrication of aluminum nitride single crystals and aluminum nitride bulk polycrystalline ceramics. Thermal treatments may also be utilized to control properties of aluminum nitride crystals after fabrication.

Abstract: Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p?GaN material on a n?GaN vertical surface extending vertically from an n?GaN horizontal surface on an n?GaN drift layer to form a first PN junction, wherein the n?GaN horizontal surface extends horizontally from the n?GaN vertical surface and the n?GaN horizontal surface has a layer of dielectric material formed on the n?GaN horizontal surface that extends from the p?GaN surface.

Abstract: We propose a method of producing a III nitride semiconductor light-emitting device 1 having a p-type semiconductor layer 150 in this order, wherein the p-type semiconductor layer 150 is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer 51 having an Al content higher than that of the barrier layer 42, on the light emitting layer 40; a nitrogen carrier gas supply step for supplying at least a carrier gas containing nitrogen as a main component to a surface of the electron blocking layer 51; and a second p-type contact formation step for forming a second p-type contact layer 55 made of AlyGa1-yN on the electron blocking layer 51 after the nitrogen carrier gas supply step, and wherein the second p-type contact formation step is performed using a carrier gas containing hydrogen as a main component.

Abstract: A semiconductor device is provided that is excellent in semiconductor properties and Schottky characteristics. A semiconductor device includes: a semiconductor layer containing a crystalline oxide semiconductor with a corundum structure as a major component; and a Schottky electrode on the semiconductor layer, wherein the Schottky electrode is formed by containing a metal of Groups 4-9 of the periodic table, thereby manufacturing a semiconductor device excellent in semiconductor properties and Schottky characteristics without impairing the semiconductor properties to use the semiconductor device thus obtained for a power device and the like.

Abstract: A method for rinsing a compound semiconductor, the method including a step of rinsing a compound semiconductor at a temperature of 80 degrees centigrade or higher with an aqueous solution of sulfuric acid of 50 wt % or less in purified water, the aqueous solution having a hydrogen ion concentration of pH 2 or less and an oxidation-reduction potential of 0.6 volts or higher, the compound semiconductor containing gallium as a constituent element, and the compound semiconductor having a surface of gallium nitride (GaN).

Abstract: Methods and structures for forming epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semi-nitrogen-polar GaN may be grown from inclined c-plane facets of sapphire and coalesced to form a continuous layer of (2021) GaN over the sapphire substrate. Nitridation of the sapphire and a low-temperature GaN buffer layer is used to form semi-nitrogen-polar GaN.

Abstract: After forming a layer of a Cu-deficient kesterite compound having the formula Cu2-xZn1+xSn(SySe1-y)4, wherein 0<x<1, and 0?y?1, on a substrate and forming a Ag layer on the Cu-deficient kesterite compound layer, the Cu-deficient kesterite compound layer and Ag layer are annealed in a S- and/or Se-rich ambient to provide a film containing a Ag—Cu mixed kesterite compound having the formula AgxCu2-xZnSn(SySe1-y)4, wherein 0<x<2, and 0?y?1.

Abstract: An encapsulated nanostructure fabricated using layers of polymer material and further processed for use in a micro-scale target device is presented. The fabrication includes the formation on a substrate of an array of encapsulated nanostructures. The encapsulated nanostructures each include a nanostructure and a micro-scale, multi-block structure that encapsulates the nanostructure. Each encapsulated nanostructure can be made usable by a target device by removing, e.g., by etching, one of the layers to expose a portion of the nanostructure.

Abstract: Electronic printing devices ink has nanoparticles of semiconducting materials with desired composition, size and band gap and modified with a volatile capping agent. Mercury cadmium telluride is synthesized by refluxing a mixture of metal salt and telluride precursor. Mercury (II) acetate and cadmium (II) acetate are reacted with a tellurium precursor (e.g. tri-n-octylphosphine telluride or telluric acid) in presence of a ligand (e.g. 1-dodecanethiol or oleylamine). This protocol yields nanoparticles of diameter ˜2-1000 nm range. The desired composition of nanoparticles is obtained by varying the relative concentration of the metal precursor. The ink is formulated by modifying the nanoparticles with volatile capping agent and dispersing the modified nanoparticles in a solvent.

Abstract: A group 13 nitride crystal has a hexagonal crystal structure and at least contains nitrogen atom and at least a kind of metal atoms selected from a group consisting of B, Al, Ga, In, and Tl. The group 13 nitride crystal includes a first region located at an inner side of a cross section intersecting a c-axis, and a second region surrounding at least a part of an outer periphery of the first region, having a thickness larger than a maximum diameter of the first region, and having a carrier density higher than that of the first region.

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.

Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

Abstract: A method of producing a metal chalcogenide dispersion usable in forming a light absorbing layer of a solar cell, the method including: a metal chalcogenide nano particle formation step in which at least one metal or metal compound selected from the group consisting of a group 11, 12, 13, 14 or 15 metal or metal compound, a water-containing solvent and a group 16 element-containing compound are mixed together to obtain metal chalcogenide nano particles; and an addition step in which a compound (1) represented by general formula (1) is added to the metal chalcogenide nano particles, thereby obtaining a metal chalcogenide dispersion (wherein R1 to R4 each independently represents an alkyl group, an aryl group or a hydrogen atom; provided that at least one of R1 to R4 represents a hydrocarbon group).

Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.

Abstract: A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: By inhibiting generation of particles, a carbon material and a method of manufacturing the carbon material are provided that can be used in the field of semiconductor manufacturing or the like, in which low dust emission is considered important. A carbon material having a chromium carbide layer formed on a surface of a carbon substrate. The chromium carbide layer is composed of Cr3C2. The carbon material can be manufactured through a first step of forming a chromium carbide layer containing a chromium carbide other than Cr3C2 on a surface of a carbon substrate, and a second step of heat-treating the carbon substrate under a reducing atmosphere to convert the chromium carbide other than Cr3C2 into Cr3C2.

Abstract: According to example embodiments, a normally-off high electron mobility transistor (HEMT) includes: a channel layer having a first nitride semiconductor, a channel supply layer on the channel layer, a source electrode and a drain electrode at sides of the channel supply layer, a depletion-forming layer on the channel supply layer, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulation layer. The channel supply layer includes a second nitride semiconductor and is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured has at least two thicknesses and is configured to form a depletion region in at least a partial region of the 2DEG. The gate electrode contacts the depletion-forming layer.

Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.

Abstract: An object of the present invention is to provide a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with AlxGa1-xN having a high Al composition, the growth temperature of which is high; a Group III nitride semiconductor growth substrate used for producing these, and a method for efficiently producing those. The present invention provides a Group III nitride semiconductor growth substrate comprising a crystal growth substrate including a surface portion composed of a Group III nitride semiconductor which contains at least Al, and a scandium nitride film formed on the surface portion are provided.

Abstract: The present disclosure regards a method for coupling a graphene layer to a substrate having at least one hydrophilic surface, the method comprising the steps of providing the substrate having at least one hydrophilic surface, depositing on the hydrophilic surface a layer of a solvent selected in the group constituted by acetone, ethyl lactate, isopropyl alcohol, methylethyl ketone and mixtures thereof and depositing on the solvent layer a graphene layer. It moreover regards an electronic device comprising the graphene/substrate structure obtained.

Abstract: All-carbon-based semiconductor devices are provided. In accordance with an example embodiment, an apparatus includes n-type and p-type carbon-based semiconductor material that form a p-n junction, which are respectively coupled to electrodes having a carbon allotrope. A first one of electrodes is connected to the n-type material and a second one of the electrodes is connected to the p-type material, and collect charge presented at the p-n junction.

Abstract: The sapphire substrate has a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device and comprising a plurality of projections of the principal surface, wherein an outer periphery of a bottom surface of each of the projections has at least one depression. This depression is in the horizontal direction. The plurality of projections are arranged so that a straight line passes through the inside of at least any one of projections when the straight line is drawn at any position in any direction in a plane including the bottom surfaces of the plurality of projections.

Abstract: An epitaxial substrate, in which a group of group-III nitride layers is formed on a single-crystal silicon substrate so that a crystal plane is approximately parallel to a substrate surface, comprises: a first group-III nitride layer formed of AlN on the base substrate; a second group-III nitride layer formed of InxxAlyyGazzN (xx+yy+zz=1, 0?xx?1, 0<yy?1 and 0<zz?1) on the first group-III nitride layer; and at least one third group-III nitride layer epitaxially-formed on the second group-III nitride layer, wherein: the first group-III nitride layer is a layer containing multiple defects including at least one type of a columnar crystal, a granular crystal, a columnar domain and a granular domain; and an interface between the first group-III nitride layer and the second group-III nitride layer is a three-dimensional asperity surface.

Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, an intermediate layer and a second electrode layer. The structural body includes a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer; the first electrode layer includes a metal portion and plural opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer, having an equivalent circular diameter not less than 10 nanometers and not more than 5 micrometers. The intermediate layer is between the first and second semiconductor layers in ohmic contact with the second semiconductor layer. The second electrode layer is electrically connected to the first semiconductor layer.

Abstract: A method for synthesizing Cu(InxGa1-x)S2 and Cu(InxGa1-x)Se2 nanopowders using flame spray pyrolysis to form solar cell absorber materials. The flame spray product is the oxide nanoparticles of the absorber materials (copper indium gallium oxide). The oxide nanoparticles may be deposited directly onto glass substrates. The oxide nanoparticles are then sulfurdized or selenized with a post deposition anneal directly on the substrate to form the absorber layer for a solar cell device.

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.

Abstract: A nitride-based semiconductor substrate has a diameter of 25 mm or more, a thickness of 250 micrometers or more, a n-type carrier concentration of 1.2×1018 cm?3 or more and 3×1019 cm?3 or less, and a thermal conductivity of 1.2 W/cmK or more and 3.5 W/cmK or less. Alternatively, the substrate has an electron mobility ? [cm2/Vs] of more than a value represented by loge ?=17.7?0.288 loge n and less than a value represented by loge ?=18.5?0.288 loge n, where the substrate has a n-type carrier concentration n [cm?3] that is 1.2×1018 cm?3 or more and 3×1019 cm?3 or less.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.

Abstract: Provided is a substrate for epitaxial growth, which enables the improvement in quality of a Ga-containing oxide layer that is formed on a ?-Ga2O3 single-crystal substrate. A substrate (1) for epitaxial growth comprises ?-Ga2O3 single crystals, wherein face (010) of the single crystals or a face that is inclined at an angle equal to or smaller than 37.5° with respect to the face (010) is the major face. A crystal laminate structure (2) comprises: the substrate (1) for epitaxial growth; and epitaxial crystals (20) which are formed on the major face (10) of the substrate (1) for epitaxial growth and each of which comprises a Ga-containing oxide.

Abstract: A method for processing a semiconductor assembly is presented. The method includes thermally processing a semiconductor assembly in a non-oxidizing atmosphere at a pressure greater than about 10 Torr. The semiconductor assembly includes a semiconductor layer disposed on a support, and the semiconductor layer includes cadmium and sulfur.

Abstract: A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.

Abstract: A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.

Abstract: A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.

Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.

Abstract: The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.

Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.

Abstract: A phase-change nonvolatile memory (PRAM) is constituted of a semiconductor substrate, a lower electrode, a first interlayer insulating film having a first hole, an impurity diffusion layer embedded in the first hole, a second interlayer insulating film having a second hole whose diameter is smaller than the diameter of the first hole, a phase-change recording layer, and an upper electrode. The impurity diffusion layer is constituted of two semiconductor layers having different conductivity types, wherein one semiconductor layer is constituted of a base portion and a projecting portion having a heating spot in contact with the phase-change recording layer, while the other semiconductor layer is formed to surround the projecting portion. A depletion layer is formed in proximity to the junction surface so as to reduce the diameter of the heating spot, thus reducing the current value Ireset for writing data in to the phase-change recording layer.