Abstract: This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer ( e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor ( e.g. silicide 40) over the substrate; a bonding layer (e.g.

Abstract: Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors.

Abstract: The vertical junction field-effect transistor comprises a semiconductor structure including an internal semiconductor layer (23, 26) extending within the channel region (7) between the gate region (4, 31), this internal layer being produced in a semiconductor material, having an energy gap (Eg.sup.2) smaller than that of the material forming the channel and gate regions, and the same type of conductivity (N) as that of the channel region, and the heterojunction formed between this internal layer and the channel region exhibits a band discontinuity situated in the valence band in the case of a N-type channel, or in the conduction band in the case of a P-type channel.

Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

Abstract: A semiconductor device which comprises: a triple-layered structure consisting of a first single-crystalline layer of a group-III--V compound semiconductor, a second single-crystalline layer of a group-IV element semiconductor, and a third single-crystalline layer of an element semiconductor interposed between the first and second layers in a manner such that coherent bond between crystal lattices is established at both interfaces between the first and third layers and between the third and second layers, the third layer preventing component elements of the first and second layers from mutually diffusing from one to the other of the first and second layers. A process according to the present invention ensures a coherent bond between crystal lattices by using an epitaxial growth.

Abstract: A Si heterojunction bipolar transistor having a SiGe narrow gap base is disclosed, in which the Ge content in the base region is higher in the neighborhood of the base-emitter junction and also in the neighborhood of the base-collector junction as compared to a central portion of the base region, and also in which the Ge concentration distribution in the base region has a slope toward the central portion from the base-emitter and the base-collector region. The Ge content in the neighborhood of the emitter-base junction can be increased up to 30 to 40%, and the emitter-base junction diffusion potential can be greatly reduced. Further, the average Ge content can be held low owing to the slope of the Ge concentration distribution, thus ensuring freedom from dislocation.

Abstract: A semiconductor device capable of reducing element sizes exceedingly and a mask alignment accuracy in lithography is provided. This device has a pair of semiconductor layers for source/drain electrodes formed on the field insulating film so as to be respectively partially projected in a "overhanging-shape" over the active area. For example, using an MBE method, a selectively epitaxial growth is made with these semiconductor layers as nuclei, so that first and second semiconductor layers at the interface of which a channel is formed and a pair of semiconductor layers for source and drain electrode connections can be formed. Accordingly, the semiconductor heterojunction and gate electrode can be formed in self-alignment on the active area with the semiconductor layers pair for source/drain electrodes as the reference, so that a reduction in transistor size can be realized.

Abstract: A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Abstract: The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

Abstract: MOS transistors are formed in thin films of Ge/Si alloys (Ge.sub.x Si.sub.1-x). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge.sub.x Si.sub.1-x films are polycrystalline at temperatures for processing down to as below 400.degree. C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600.degree. C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400.degree. to 500.degree. C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500.degree. C.

Abstract: A semiconductor device includes a first neutral impurity layer formed to a predetermined depth from a surface of a semiconductor substrate in a channel region that is interposed between source/drain regions and located below a gate electrode, and a second neutral impurity layer having a higher concentration than that of the first neutral impurity layer and formed to surround lower portions of the source/drain regions except for the channel region. Scattering of neutral impurities in the first neutral impurity layer suppresses generation of hot carriers, and the second neutral impurity layer suppresses diffusion of impurities in the source/drain regions in thermal processing. The second neutral impurity layer is formed by implanting neutral impurities obliquely after formation of the gate electrode.

Abstract: A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.

Abstract: A semiconductor device including a single crystal semiconductor host material having a surface; an ultrathin pseudomorphic single crystal epitaxial interlayer formed on the surface of the host material, wherein the interlayer is formed of a material and has a thickness selected so that the material of the interlayer is elastically deformed on the surface of the host material to match the lattice constant of the interlayer material with the lattice constant of the host material; and a further material incompatible with the host material when interfaced directly with the host material, but compatible with the interlayer, provided on the interlayer and thereby interfaced with the host material to perform a predetermined function with respect to the interlayer and the host material.