Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an inter-layer insulating film, a wiring, and a via. The inter-layer insulating film is provided on the semiconductor substrate. The wiring is provided in the inter-layer insulating film. The via is provided in the inter-layer insulating film. Inside the inter-layer insulating film in a circumferential region around a device region, a vertical structure body is formed in which the wiring and the via are vertically connected. At least in an upper portion inside the inter-layer insulating film in an edge region located around the circumferential region and constituting an outer edge portion, no vertical structure body is formed in which the wiring and the via are vertically connected.

Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

Abstract: A semiconductor device includes a substrate having a circuit formation region, an interlayer insulating film formed on the substrate, a first seal ring formed in the interlayer insulating film to surround the circuit formation region, a first protective film formed on the interlayer insulating film in the circuit formation region and on the first seal ring, and a second protective film formed on the first protective film and inside relative to the first seal ring. The first protective film has a first surface contacting the second protective film, a second surface located directly on the first seal ring, and a third surface connecting the first surface and the second surface together, and an end of the second protective film is located inside relative to the third surface.

Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor wafer that has plural semiconductor chips. Each of the plural semiconductor chips includes a first principal side and a second and opposite principal side. Material is removed from the semiconductor wafer to define at least one rounded corner of the first principal side of at least one of the plural semiconductor chips.

Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.

Abstract: A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes.

Abstract: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.

Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

Abstract: To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off.

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Abstract: The disclosed WLCSP solution overcomes the limitations of fan-out WLCSP solutions, and other conventional solutions for WLCSP for small, high volume die, by increasing the width of scribe regions between die on a semiconductor substrate to accommodate bonding structures (e.g., solder balls) that partially extend beyond peripheral edges of the die. The scribe regions can be widened in x and y directions on the wafer. The widened scribe regions can be incorporated into the design of the mask set.

Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract: An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.

Abstract: A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process.

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Abstract: An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks for providing an electrical connection from the active front face to the passive rear face. An electronic assembly formed of stacked semiconductor chips, and a method for producing the electronic component and the electronic assembly are also provided.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate having an element formation region and a dicing region; an element layer over the element formation region and the dicing region; and a multi-layered wiring structure over the dicing region. The multi-layered wiring structure extends upwardly from the element layer. The multi-layered wiring structure has a groove penetrating the multi-layered wiring structure.

Abstract: Provided is a laminated film wherein the space between semiconductor elements that are three-dimensionally mounted can be filled easily and securely. The laminated film of the present invention is a laminated film for filling the space between semiconductor elements that are electrically connected through a member or connection, the film including a dicing sheet in which a pressure-sensitive adhesive layer is laminated on a base material and a curable film that is laminated on the pressure-sensitive adhesive layer, wherein the curable film has a lowest melt viscosity at 50 to 200° C. of 1×102 Pa·s or more and 1×104 Pa·s or less.

Abstract: Provided is an inverter-integrated motor including a motor and an inverter integrated in an efficient manner. Also provided is a semiconductor chip that can be used in this motor. An IGBT chip is constructed with an emitter terminal being provided at the apex of one face of a die having a regular triangular surface shape, a gate terminal being provided adjacent the opposite side to the apex, and a collector terminal being provided on the other face. A power semiconductor module is constructed with placing apices of the IGBT chips having the emitter terminals in abutment against each other. Six such power semiconductor chips are arranged in a regular hexagonal pattern to together constitute an inverter for converting DC power into three-phase AC power.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.

Abstract: An integrated circuit is disclosed with adjusting elements, which in a first manufacturing stage are connected via tracks to terminal pads lying outside the integrated circuit. At least one of the tracks of the integrated circuit lies on a surface of a region, which includes semiconductor material and in a second manufacturing stage is isolated by a pn junction from additional semiconductor material, which is adjacent to the region. Furthermore, a method for manufacturing this type of integrated circuit is also disclosed.

Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

Abstract: The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract: A semiconductor wafer 10 has a plurality of semiconductor chip areas 10a and a scribe area 10b, each of the semiconductor chip areas 10a having semiconductor elements and electrode pads (electrode portions) 16a electrically connected to the respective semiconductor elements, the scribe area 10b having monitor elements and electrode pads (electrode portions) 16b electrically connected to the monitor elements, wherein projecting electrodes 18 are selectively formed only on the respective electrode pads 16a in the semiconductor chip areas 10a by electroless plating. Thus, for example, the electrode pads 16b are covered with an insulating film 14.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.

Abstract: A method for increasing semiconductor device effective operation area, comprising following steps: depositing first conductive layer on the substrate; using laser for scribing a plurality of the first scribe lines on the first conductive layer, where the scribe lines are scribed on the bottom of the first conductive layer; depositing a plurality of the semiconductor material layers on the first conductive layer and in the plurality of the first scribe lines; using laser for scribing a plurality of the second scribe lines on the semiconductor material layer, where the scribe lines are scribed on the bottom of the semiconductor material layer, each second scribe line is comprised of a plurality of the second pores; depositing a second conductive layer on the semiconductor material layer and in the plurality of the first scribe lines and the plurality of the second scribe lines; using laser for scribing a plurality of the third scribe lines on the second conductive layer, where the scribe lines are scribed on th

Abstract: Devices and methods for pattern alignment are disclosed. In one embodiment, a semiconductor device includes a die including an integrated circuit region, an assembly isolation region around the integrated circuit region, and a seal ring region around the assembly isolation region. The device further includes a die alignment mark disposed within the seal ring region or the assembly isolation region.

Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: A semiconductor chip module includes a chip unit including at least two semiconductor chips disposed with a scribe lane interposed therebetween and each of which has a first surface on which bonding pads are disposed and a second surface that faces away from the first surface. Redistribution lines formed on the first surface of each semiconductor chip have first ends, which are connected with the bonding pads of each semiconductor chip, and second ends that extend to and are disposed on the scribe lane. Through electrodes formed to pass through the scribe lane are electrically connected with the second ends of the redistribution lines.

Abstract: In one embodiment, a method is provided for packaging a semiconductor die. A leadframe having a die-pad and one or more lead-pads is placed (502) on an assembly surface. The die-pad has a base portion (202) resting on the assembly surface, an upper portion (204) on the base portion extending laterally from the base portion, and a support arm (208) extending from and supporting the upper portion of die-pad. A semiconductor die (206) is wirebonded (504) to a top surface of the upper portion of the die-pad. The semiconductor die is wirebonded (506) to the one or more lead-pads (210). The semiconductor die and leadframe are encased (508) in a package material (802). The package material fills a space between the upper portion of the die-pad and the assembly surface. A portion of the support arm located in a cutting lane is removed (512).

Abstract: Disclosed herein is a semiconductor device having a novel stress reduction structures that are employed in an effort to eliminate or at least reduce undesirable cracking or chipping of semiconductor die. In one example, the device includes a die comprising a semiconducting substrate, wherein the die includes a cut surface. The device also includes a first die seal that defines a perimeter, and at least one stress reducing structure, at least a portion of which is positioned between the perimeter defined by the first die seal and the cut surface, wherein the cut surface exposes at least a portion of the stress reducing structure.

Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

Abstract: In a wafer, a first chip region and a second chip region are separated from each other by a dicing region. The dicing region includes: a first center region; a first intermediate region located on the first chip region's side of the first center region; a second intermediate region located on the second chip region's side of the first center region; a first outer region located on the first chip region's side of the first intermediate region; and a second outer region located on the second chip region's side of the second intermediate region. Surfaces of the first and second intermediate regions are respectively covered by bank-shaped resin films extending in a longitudinal direction of the dicing region. Respective surfaces of the first center region, the first outer region and the second outer region are not covered by resin films.

Abstract: Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate.

Abstract: A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.