Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.

Abstract: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

Abstract: According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.

Abstract: A mold (10) including a first mold part (12) and a second mold part (14) define a mold cavity (16) therebetween. A gate (18) is formed in at least one of the first and second mold parts (12) and (14) such that the gate (18) communicates with the mold cavity (16). A vent (20) having a constricted portion (22) is arranged to communicate with the mold cavity (16). A substrate (28) including a base substrate (30) and an electrically conductive pattern (32) and (34) formed on the base substrate (30) may be received in the mold (10). A solder resist layer (36) is formed on the base substrate (30) and a portion of the electrically conductive pattern (32). A plurality of grooves (38) and (40) is formed in a staggered arrangement around a periphery of a molding area (42) on the substrate (28).

Abstract: A silicon substrate has a protective film formed on each side. A semiconductor surface opening not smaller than a given region is formed by removing the protective film. A through-hole having an inner size smaller than the given region is formed in the opening by laser machining. Thereafter, the inner size of the through-hole is increased by anisotropic etching, and the etching is ended when the inner size of the through-hole reaches the given size. In this way, a through-hole of a given size can be formed without allowing reversely tapered crystal planes to appear from a surface of the substrate toward the inside of the through-hole.

Abstract: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Abstract: The present invention provides a semiconductor chip that provides a semiconductor device with high reliability and low leak current, and a method of manufacturing such a semiconductor chip, and more specifically, provides a semiconductor chip comprising memory portions and a peripheral circuit portion, where the memory portions and the peripheral circuit portion are formed in a main surface portion of the semiconductor chip, a thickness of the sections of the semiconductor chip passing through the main surface portion in which the memory portions are formed is larger than a thickness of sections of the semiconductor chip passing through the main surface portion in which the peripheral circuit portion is formed, and a method of manufacturing such a semiconductor chip.

Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Abstract: A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the basis of programming information, and a read circuit (40) reading the programming information by determining whether such an opening (21) is formed in the program layer (20) by utilizing an electrostatic capacitance between the pair of metal interconnections (B, C). The program layer (20) may be made of a material having a dielectric constant higher than that of air or the program layer (20) may be made of a conductor or a material having a dielectric constant lower than that of air.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface (5) of a collector region (2) and a base region (3) is formed of a mesa groove (6) made of a trench. Thus, the chip size is not increased even when the mesa groove (6) is deeply formed to increase the breakdown voltage.

Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.

Abstract: An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.

Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.

Abstract: A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.

Abstract: A semiconductor device includes: a substrate having a main surface, a rear surface and four side surfaces; a semiconductor element formed on the main surface of the substrate; a notch formed in at least one bottom part of the side surfaces of the substrate; and a curved surface provided at an intersection of a side surface of the notch and the rear surface of the substrate.

Abstract: The invention generally relates to semiconductor device processing, and more particularly to methods of accessing semiconductor circuits from the backside using ion-beam and gas-etch to mill deep vias through full-thickness silicon. A method includes creating a pocket in a material to be etched, and performing an isotropic etch of the material by flowing a reactive gas into the pocket and directing a focused ion beam into the pocket.

Abstract: A semiconductor device including a semiconductor substrate having a plurality of electrodes, a resin protrusion formed on the semiconductor substrate, and an interconnect electrically connected to the electrodes and formed to extend over the resin protrusion. A depression is formed in a top surface of the resin protrusion. The interconnect has a cut portion disposed over at least part of the depression.

Abstract: A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process.

Abstract: There is disclosed a hybrid circuit in which a circuit formed of TFTs in integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.

Abstract: A substrate for a light emitting diode (LED) can have one or more trenches formed therein so as to mitigate stress build up within the substrate due to mismatched thermal coefficients of expansion between the substrate and layers of material, e.g., semiconductor material, formed thereon. In this manner, the likelihood of damage to the substrate, such as cracking thereof, is substantially mitigated.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g.

Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.

Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: The present invention relates to a method of fabricating a nanogap and a nanogap sensor, and to a nanogap and a nanogap sensor fabricated using the method. The present invention relates to a method of fabricating a nanogap and a nanogap sensor, which can be realized by an anisotropic etching using a semiconductor manufacturing process. According to the method of present invention, the nanogap and nanogap sensor can be simply and cheaply produced in large quantities.

Abstract: A method is provided for fabricating a semiconductor device. The method begins by forming on a substrate an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate. After forming the interconnect stack layer, a crack stop trench is formed in the interconnect stack layer. Finally, the crack stop trench is filled with a prescribed material.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.

Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.

Abstract: An attachment system. The attachment system includes a first structure and a second structure. The first structure has a surface and a recess in the surface. The second structure is molded into the recess and extends above the surface. The second structure adheres to the first structure at a boundary of the recess.

Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.

Abstract: A semiconductor device capable of preventing damage to a thermal oxide layer in a trench, and a method for fabricating the same are disclosed. The device includes a trench in a field region of a semiconductor substrate; a pad oxide layer on the surface of the semiconductor substrate outside the trench; a thermal oxide layer on sidewalls of the trench; a nitride layer covering the thermal oxide layer; an insulating layer filling the trench; and a spacer covering the thermal oxide layer outside the trench.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.

Abstract: Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.

Abstract: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Abstract: A process for digging deep trenches in a body of semiconductor material includes forming a mask having an opening, above a surface of a semiconductor body. A passivating layer is conformally formed on the mask and on the semiconductor body within the opening. A directional etch is extended to first remove the passivating layer from on top of the semiconductor body and then etch the semiconductor body through the opening. Forming the passivating layer and executing the directional etch are carried out repeatedly in sequence so as to form a trench through the opening. A tapered portion of the trench is formed, which has a transverse dimension decreasing as a distance from the surface of the semiconductor body increases.

Abstract: A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form embedded spacers. Conventional source/drain regions may then be formed.

Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

Abstract: A wafer (W) comprises i) at least one independent die (D1, D2) having internal integrated components (IC), a multiplicity of internal pads (IP1-IP3) connected to some of the internal integrated components (IC), ii) scribe lanes (SL) defined between and around each independent die (Di), and in part of which are defined, for each die (D1, D2), at least a first group (G11, G12) of external pads (EP1-EP3) and/or a second group of external test integrated components (EC). The external pads (EP1-EP3) of each first group (G11, G12) are connected, through conductive tracks, to a chosen one of the internal pads (IP1-IP3) and/or internal integrated components (IC) of the associated die (D1, D2), and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components (IC) and/or to external pads of a first group.

Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Abstract: A method of fabricating an integrated circuit is disclosed. An etching process is performed in order to create a structure in a substrate. A material layer is generated during the etching process. The material layer is formed from at least one of the group of a Si/C/O composition and/or a Si/metal composition.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.