Abstract: A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.

Abstract: A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device.

Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.

Abstract: Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: A semiconductor wafer having a disc shape includes a chamfer provided around a circumferential edge of the wafer, and an anti-cracking and chipping groove provided in one or more areas around one circumference of an end face of the wafer along a circumferential direction of the end face. The anti-cracking and chipping groove is configured to prevent cracking or chipping of the end face in back grinding.

Abstract: A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.

Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.

Abstract: The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates.

Abstract: A semiconductor substrate is coated with a single layer of different materials selected from adhesives, coatings, and encapsulants.

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: An assembly (220) includes a MEMS die (222) and an integrated circuit (IC) die (224) attached to a substrate (226). The MEMS die (222) includes a MEMS device (237) formed on a substrate (242). A packaging process (264) entails forming the MEMS device (237) on the substrate (242) and removing a material portion of the substrate (237) surrounding the device (237) to form a cantilevered substrate platform (246) suspended above the substrate (226) at which the MEMS device (237) resides. The MEMS die (222) is electrically interconnected with the IC die (224). A plug element (314) can be positioned overlying the platform (246). Molding compound (32) is applied to encapsulate the die (222), the IC die (224), and substrate (226). Following encapsulation, the plug element (314) can be removed, and a cap (236) can be coupled to the substrate (242) overlying an active region (244) of the MEMS device (237).

Abstract: A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.

Abstract: Ultra-thin semiconductor devices, including piezo-resistive sensing elements can be formed a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes.

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.

Abstract: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46).

Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

Abstract: A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.

Abstract: A semiconductor device (10), comprising a first semiconductor portion (32) having a first end (34), a second end (36), and a slit portion (30), wherein the width of the slit portion (30) is less than the width of at least one of the first end (34) and the second end (36); a second portion (38) that is a different material than the first semiconductor portion (32), a third portion (40) that is a different material than the first semiconductor portion (32), wherein the second (38) and third (40) portions are on opposite sides of the slit portion (30), and at least three terminals selected from a group consisting of a first terminal (12) connected to the first end (34), a second terminal (14) connected to the second end (36), a third terminal (16) connected to the second portion (38), and a fourth terminal (17) connected to the third portion (40).

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract: A semiconductor device includes: element formation regions each including a cell region where a semiconductor element is formed, a termination trench region; and a dicing line region including a groove separating the element formation regions. The termination trench region includes four trenches surrounding four sides of the cell region. Two of the trenches extend longitudinally in parallel to an X direction and the other two trenches extend longitudinally in parallel to a Y direction perpendicular to the X direction. The termination trench region is perpendicularly in contact with longitudinal sides of the dicing line region while the trenches extending longitudinally in parallel to the X direction intersect the trenches extending longitudinally in parallel to the Y direction at four corners of the element formation region, while vertical sections of the termination trench region in a cross direction are opened in four side surfaces of the element formation region.

Abstract: An epitaxy substrate for growing a plurality of semiconductor epitaxial layers thereon, includes a plurality of growth areas and a plurality of protected areas. The growth areas are provided for growing the semiconductor epitaxial layers thereon. The growth areas and the protected areas are alternating. A thickness of the growth areas is less than ? of a thickness H of the protected areas.

Abstract: A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle ? in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.

Abstract: A lithographic material stack including a photo-resist and an organic planarizing layer is combined with an etch process that generates etch residues over a wide region from sidewalls of etched regions. By selecting the etch chemistry that produces deposition of etch residues from the organic planarizing layer over a wide region, the etch residue generated at the sidewalls of the wide trench is deposited over the entire bottom surface of the wide trench. An etch residue portion remains at the bottom surface of the wide trench when the organic planarizing layer is etched through in the first trench region. The etch residue portion is employed in the next step of the etch process to retard the etch rate in the wide trench, thereby producing the same depth for all trenches in the material layer into which the pattern of the lithographic material stack is transferred.

Abstract: A component-containing module includes a core substrate which includes a lower surface including recessed portions and a raised portion, and an upper surface facing the lower surface and which includes a plurality of in-plane conductors, an integrated circuit element arranged at a location which is above the upper surface and which corresponds to the raised portion, a first passive element and a second passive element disposed in the recessed portions of the lower surface, a composite resin layer which underlies the lower surface and which has a flat or substantially flat surface, and an external terminal electrode which is disposed on the flat or substantially flat surface of the composite resin layer and which is electrically connected to the in-plane conductors of the core substrate. The component-containing module enables electronic components, such as integrated circuit elements and passive elements, to be densely arranged and to be reduced in profile and size.

Abstract: The present invention provides a dicing die bond film in which peeling electrification hardly occurs and which has good tackiness and workability. The dicing die bond film of the present invention is a dicing die bond film including a dicing film and a thermosetting type die bond film provided thereon, wherein the thermosetting type die bond film contains conductive particles, the volume resistivity of the thermosetting type die bond film is 1×10?6 ?·cm or more and 1×10?3 ?·cm or less, and the tensile storage modulus of the thermosetting type die bond film at ?20° C. before thermal curing is 0.1 to 10 GPa.

Abstract: A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a first insulating film; and a first semiconductor film. The semiconductor substrate has a groove defining a first portion of the semiconductor substrate. The first portion extends upward. The first insulating film fills the groove. The first insulating film has a recess adjacent to a side surface of the first portion. The first semiconductor film contacts an upper surface and the side surface of the first portion.

Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.

Abstract: Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO2), diamond-like carbon, graphene, and silicon carbide (SiC) of a predetermined phase. In accordance with still another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a multi-layer film is disposed at the substrate surface and spans the isotropically defined cavity.

Abstract: Materials that contain liquid are deposited into grooves upon a surface of a work piece, such as a silicon wafer to form a solar cell. Liquid can be dispensed into work piece paths, such as grooves under pressure through a dispensing tube. The tube mechanically tracks in the groove. The tube may be small and rest at the groove bottom, with the sidewalls providing restraint. Or it may be larger and ride on the top edges of the groove. A tracking feature, such as a protrusion, Non-circular cross-sections, molded-on protrusions and lobes also enhance tracking. The tube may be forced against the groove by spring or magnetic loading. Alignment guides, such as lead-in features may guide the tube into the groove. Restoring features along the path may restore a wayward tube. Many tubes may be used. Many work pieces can be treated in a line or on a drum.

Abstract: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.

Abstract: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.

Abstract: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

Abstract: A method for manufacturing a semiconductor device is provided with: a step of preparing a semiconductor wafer (22) in a state where the circumference of the semiconductor wafer, which has been divided into semiconductor device parts, is adhered on a dicing sheet (21) supported by a wafer ring (23); a step of fixing the wafer ring (23) after transferring the wafer ring to a table (14) where laser printing is to be performed; and a step of marking on the main surface where the semiconductor material of the semiconductor device parts which configure the semiconductor wafer (22) is exposed, by radiating laser beams through the dicing sheet and an adhesive layer.

Abstract: A vent hole precursor structure (26) in an intermediate product for a semi-conductor device has delicate structures (27, 28), and said intermediate product has a cavity (21) with a pressure therein differing from the pressure of the surroundings. The intermediate product comprises a first wafer (20) in which there is formed a depression (21). The first wafer is bonded to a second wafer (22) comprising a device layer (23) from which the structures (27, 28) are to be made by etching. A hole or groove (26) having a predefined depth extends downwards into the device layer, such that the cavity (21) during etching is opened up before the etching procedure breaks through the device layer (23) to form the structures (27, 28).

Abstract: A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Abstract: Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate (101) and a second circuit substrate (102) which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate (101) and the peripheral portion of the second circuit substrate (102) are connected to each other by connection members (10a to 10d) having a wiring member (103) and a thermal hardening anisotropic conductive sheet (107), thereby performing electric connection.

Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.

Abstract: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.

Abstract: The present invention relates to a carbon ribbon for covering in a thin layer of semiconductor material, and to a method of deposited such a layer on a substrate constituted by a carbon ribbon. At least one of the two faces of the carbon ribbon is for covering in a layer of semiconductor material by causing the ribbon to pass substantially vertically upwards through a bath of molten semiconductor material. According to the invention, the two edges of at least one of the two faces of the carbon ribbon project so as to form respective rims.

Abstract: An apparatus (100) for fabricating a semiconductor thin film includes: substrate surface pretreatment means (101) for pretreating a surface of a substrate; organic layer coating means (102) for coating, with an organic layer, the substrate thus pretreated; focused light irradiation means (103) for irradiating, with focused light, the substrate coated with the organic layer, and for forming a growth-mask layer while controlling layer thickness; first thin film growth means (104) for selectively growing a semiconductor thin film over an area around the growth-mask layer; substrate surface treatment means (105) for, after exposing the surface of the substrate by removing the growth-mask layer, modifying the exposed surface of the substrate; and second thin film growth means (106) for further growing the semiconductor thin film and growing a semiconductor thin film over the modified surface of the substrate.

Abstract: An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided.

Abstract: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.