With Inversion-preventing Shield Electrode Patents (Class 257/630)
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Patent number: 10903177Abstract: In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.Type: GrantFiled: July 15, 2019Date of Patent: January 26, 2021Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Se-Jin Yoo, Hong-Sub Joo, Won-Gil Han
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Patent number: 10741541Abstract: A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes simultaneously forming a gate oxide layer of a transistor device and transforming the amorphous silicon layer into a polycrystalline silicon layer by a thermal oxidation process. Herein a cover oxide layer is formed on the polycrystalline silicon layer.Type: GrantFiled: October 4, 2016Date of Patent: August 11, 2020Assignee: Infineon Technologies Dresden GmbHInventors: Joachim Weyers, Markus Schmitt, Armin Tilke, Stefan Tegen, Thomas Bertrams
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Patent number: 10192981Abstract: A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer. a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.Type: GrantFiled: March 3, 2017Date of Patent: January 29, 2019Assignee: POWER INTEGRATIONS, INC.Inventors: Alexey Kudymov, Jamal Ramdani
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Patent number: 9576791Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure. An electrically semi-insulating passivation layer overlies the semiconductor structure. An electrically substantially fully insulating passivation layer overlies the electrically semi-insulating passivation layer.Type: GrantFiled: June 1, 2015Date of Patent: February 21, 2017Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Craig J. Atkinson, Alireza Amirrezvani, Nicole C. Skaggs
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Patent number: 9564427Abstract: An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.Type: GrantFiled: January 15, 2016Date of Patent: February 7, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Mahalingam Nandakumar
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Patent number: 8853778Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.Type: GrantFiled: August 27, 2012Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventor: Toru Tanzawa
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Patent number: 8796802Abstract: Semiconductor photodetectors are provided that may enable optimized usage of an active detector array. The semiconductor photodetectors may have a structure that can be produced and/or configured as simply as possible. A radiation detector system is also provided.Type: GrantFiled: October 13, 2010Date of Patent: August 5, 2014Assignee: First Sensor AGInventors: Michael Pierschel, Frank Kudella
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Patent number: 8674471Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.Type: GrantFiled: August 28, 2012Date of Patent: March 18, 2014Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 8552535Abstract: A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.Type: GrantFiled: November 14, 2008Date of Patent: October 8, 2013Assignee: Semiconductor Components Industries, LLCInventors: Peter A. Burke, Brian Pratt, Prasad Venkatraman
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Patent number: 8502311Abstract: It is disclosed a semiconductor transistor, comprising a semiconductor substrate (111) in which a channel region (115) and a drain extension region (119) connected to the channel region are provided; a gate electrode (127) configured to provide an electric field for influencing the channel region; a first electrically conductive shield element (131) extending in a horizontal direction (103) parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region in a vertical direction (105) perpendicular to the horizontal direction; and a second electrically conductive shield element (133) arranged spaced apart from the first shield element in the vertical direction, wherein the gate electrode protrudes over the first shield element in the vertical direction.Type: GrantFiled: April 25, 2011Date of Patent: August 6, 2013Assignee: NXP B.V.Inventor: Stephan Jo Cecile Henri Theeuwen
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Patent number: 8120107Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.Type: GrantFiled: January 13, 2011Date of Patent: February 21, 2012Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 8110888Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.Type: GrantFiled: September 9, 2008Date of Patent: February 7, 2012Assignee: Microsemi CorporationInventors: Jinshu Zhang, Dumitru Sdrulla, Dah Wen Tsang
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Patent number: 7919836Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.Type: GrantFiled: April 24, 2009Date of Patent: April 5, 2011Assignee: Renesas Electronics CorporationInventor: Yasutaka Nakashiba
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Patent number: 7898029Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.Type: GrantFiled: June 8, 2009Date of Patent: March 1, 2011Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 7893439Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.Type: GrantFiled: January 4, 2008Date of Patent: February 22, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Shunpei Yamazaki, Kengo Akimoto
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Patent number: 7875914Abstract: Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.Type: GrantFiled: May 29, 2009Date of Patent: January 25, 2011Assignee: Cree, Inc.Inventor: Scott Sheppard
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Patent number: 7808033Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.Type: GrantFiled: July 27, 2006Date of Patent: October 5, 2010Inventor: Yoshihiro Kumazaki
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Patent number: 7741662Abstract: An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.Type: GrantFiled: October 15, 2008Date of Patent: June 22, 2010Assignee: United Microelectronics Corp.Inventor: Ching-Hung Kao
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Publication number: 20100123220Abstract: A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.Type: ApplicationFiled: November 14, 2008Publication date: May 20, 2010Inventors: Peter A. Burke, Brian Pratt, Prasad Venkatraman
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Patent number: 7576414Abstract: A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage.Type: GrantFiled: November 2, 2007Date of Patent: August 18, 2009Assignee: STATS ChipPAC, Ltd.Inventors: Rui Huang, Yaojian Lin, Seng Guan Chow
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Patent number: 7548112Abstract: Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.Type: GrantFiled: July 21, 2005Date of Patent: June 16, 2009Assignee: Cree, Inc.Inventor: Scott Sheppard
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Patent number: 7545025Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.Type: GrantFiled: March 3, 2008Date of Patent: June 9, 2009Assignee: NEC Electronics CorporationInventor: Yasutaka Nakashiba
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Patent number: 7525178Abstract: A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed to prevent direct electrical contact between the field rings and the field plate such that the at least one field ring is capacitively coupled with the at least one field plate. Such a termination region may also include a polysilicon plate capacitively coupled with a diffusion region laterally spaced from the field rings, the polysilicon plate being located at an outer surface or directly under a passivation layer at an outer surface of the die. The termination region may also include floating field rings. The insulation layer may be a field oxide layer.Type: GrantFiled: October 25, 2006Date of Patent: April 28, 2009Assignee: International Rectifier CorporationInventor: Lawrence Kulinsky
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Patent number: 7473974Abstract: A protection element comprises a ring-shape gate electrode, an N+ drain region inside the ring-shape gate electrode, an N+ source region outside, and a shield plate electrode. The ring gate and source regions are connected to ground via a through-hole, and the drain region is connected to an external pad. The shield plate electrode is connected to ground or to a power supply. Element isolation is achieved by the shield plate electrode, without forming a LOCOS or other element isolation oxide layer. By this means, blocking of thermal conduction by an oxide layer can be avoided to improve the heat dissipation and ESD resistance of the protection element.Type: GrantFiled: June 1, 2004Date of Patent: January 6, 2009Assignee: NEC Electronics CorporationInventor: Hiroshi Furuta
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Patent number: 7456451Abstract: An ultra high voltage MOS transistor device includes a substrate of a first conductivity type; a source region of a second conductivity type formed in the substrate; a first doping region of the first conductivity type formed in the substrate and bordering upon the source region; a first ion well of the first conductivity type encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region of the second conductivity type formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well of the second conductivity type encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.Type: GrantFiled: September 13, 2005Date of Patent: November 25, 2008Assignee: United Microelectronics Corp.Inventor: Ching-Hung Kao
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Patent number: 7307314Abstract: A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.Type: GrantFiled: June 16, 2004Date of Patent: December 11, 2007Assignee: Cree Microwave LLCInventors: Jeff Babcock, Johan Agus Darmawan, John Mason, Ly Diep
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Publication number: 20070241429Abstract: An electrically conducting track comprising an electrically conducting track layer; a semiconductor substrate; and a dielectric layer sandwiched between track layer and semiconductor substrate; the electrically conducting track further comprising an electrically conducting resistor track between semiconductor substrate and dielectric layerType: ApplicationFiled: April 18, 2007Publication date: October 18, 2007Applicant: FILTRONIC COMPOUND SEMICONDUCTORS LIMITEDInventors: Ron Arnold, John Stephen Atherton, Nigel Cameron, Matthew Francis O'Keefe
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Patent number: 7227214Abstract: A lower electrode of a capacitor element and a wiring are formed in a wiring layer that is one layer below an uppermost wiring layer. Subsequently, after the formation of a capacitance insulating film, a TiN film is formed on the entire surface thereof, and then the TiN film is patterned, thereby forming an upper electrode of a capacitor element and a lead wiring for electrically connecting the upper electrode to a wiring of a third wiring layer. Furthermore, in the uppermost layer, a shield is formed covering the upper portion of the capacitor element.Type: GrantFiled: April 2, 2002Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Osamu Kobayashi, Akiyoshi Watanabe
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Patent number: 7071530Abstract: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.Type: GrantFiled: January 27, 2005Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu
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Patent number: 7029981Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.Type: GrantFiled: June 25, 2004Date of Patent: April 18, 2006Assignee: Intersil Americas, Inc.Inventors: Nicolaas W. van Vonno, Dustin Woodbury
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Patent number: 6998679Abstract: A semiconductor device includes a gate electrode on a semiconductor substrate, a source electrode and a drain electrode that are provided on the semiconductor substrate, the gate electrode being interposed between the source electrode and the drain electrode, an insulating layer covering the gate electrode, and a source wall that extends from the source electrode and passes over the gate electrode, an end surface of the source wall being interposed between the gate electrode and the drain electrode and being located in a position lower than a top surface of the gate electrode.Type: GrantFiled: January 23, 2003Date of Patent: February 14, 2006Assignee: Fujitsu Quantum Devices LimitedInventors: Kazutaka Inoue, Hitoshi Haematsu
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Patent number: 6940151Abstract: A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1.5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.Type: GrantFiled: September 30, 2002Date of Patent: September 6, 2005Assignee: Agere Systems, Inc.Inventors: Michael Scott Carroll, Yi Ma, Minesh Amrat Patel, Peyman Sana
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Patent number: 6917076Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.Type: GrantFiled: July 31, 2003Date of Patent: July 12, 2005Assignee: United Microelectronics CorporationInventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
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Patent number: 6882014Abstract: A protection circuit for MOS components. In the protection circuit, a bypass PMOS transistor has a gate, a source and a substrate, all coupled to a first voltage node and a drain coupled to a gate of a MOS component. A bypass NMOS transistor has a gate, a source and a substrate, all coupled to a second voltage node and a drain coupled to the gate of the MOS component. When positive charges are accumulated on the gate of the MOS component due to an antenna effect, the bypass PMOS transistor dissipates the positive charges to the first voltage node. On the contrary, when negative charges are accumulated on the gate of the MOS component due to antenna effect, the bypass NMOS transistor dissipates the negative charges to the second voltage node.Type: GrantFiled: August 16, 2001Date of Patent: April 19, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chih-Ping Tan
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Patent number: 6838770Abstract: A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.Type: GrantFiled: June 27, 2001Date of Patent: January 4, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Niichi Itoh
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Patent number: 6797991Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.Type: GrantFiled: June 12, 2003Date of Patent: September 28, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masahiro Ishida
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Patent number: 6777767Abstract: A crystalline substrate based device includes a crystalline substrate having formed thereon a microstructure, and a transparent packaging layer which is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the packaging layer. The microstructure receives light via the transparent packaging layer.Type: GrantFiled: November 29, 2000Date of Patent: August 17, 2004Assignee: Shellcase Ltd.Inventor: Avner Pierre Badehi
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Publication number: 20040150073Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.Type: ApplicationFiled: January 9, 2004Publication date: August 5, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Akira Matumoto, Tadashi Fukase, Manabu Iguchi, Masahiro Komuro
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Patent number: 6765266Abstract: In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.Type: GrantFiled: December 3, 2002Date of Patent: July 20, 2004Assignee: Denso CorporationInventors: Yoshihiko Ozeki, Yutaka Tomatsu, Norihito Tokura, Haruo Kawakita
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Patent number: 6756619Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: August 26, 2002Date of Patent: June 29, 2004Assignee: Micron Technology, Inc.Inventor: Luan C. Tran
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Publication number: 20040051166Abstract: A shielding line system reduces or eliminates crosstalk between conductive lines in an integrated circuit. The shielding line system has first conductive line and one or more second conductive lines. A shielding line conduit radially encloses the first conductive line. An electromagnetic field also radially encloses the first conductive line.Type: ApplicationFiled: September 18, 2002Publication date: March 18, 2004Inventors: Guenter Gerstmeier, Torsten Partsch
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Patent number: 6653663Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.Type: GrantFiled: December 5, 2000Date of Patent: November 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masahiro Ishida
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Publication number: 20030207477Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: ApplicationFiled: October 25, 2002Publication date: November 6, 2003Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Patent number: 6642551Abstract: A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.Type: GrantFiled: August 23, 2001Date of Patent: November 4, 2003Assignee: IXYS CorporationInventor: Nathan Zommer
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Patent number: 6597053Abstract: An integrated circuit arrangement having a number of structural elements, at least one of which is surrounded by a metallic shielding structure. This structural element is thus protected against interference due to disturbing impulses from its environment. In particular, the structural elements of the circuit arrangement can be arranged next to or on top of one another. To produce the metallic shielding structure of a structural element of the circuit arrangement, at least one depression which surrounds the structural element is created and then lined with metal. The contacts and electrical connections of the structural element are electrically insulated from the metal of the shielding structure.Type: GrantFiled: October 15, 1999Date of Patent: July 22, 2003Assignee: Siemens AktiengesellschaftInventors: Anton Anthofer, Holger Hübner
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Patent number: 6563197Abstract: Guard ring diffusions in the termination of a MOSgated device are laterally spaced from one another and are disposed beneath and are insulated from the termination field plate which extends from the periphery of the device active area.Type: GrantFiled: November 20, 2001Date of Patent: May 13, 2003Assignee: International Rectifier CorporationInventors: Kenneth Wagers, Yanping Ma, Jianjun Cao
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Patent number: 6515349Abstract: The main purpose is to provide a semiconductor device which has a field plate wherein the electric field concentration at a step part can be eliminated and a higher withstanding voltage can be gained. A field plate is provided on a substrate. The field plate has a step part which bends toward the downward direction from the surface of the substrate.Type: GrantFiled: March 7, 2001Date of Patent: February 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tomohide Terashima
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Patent number: 6504185Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.Type: GrantFiled: June 5, 2001Date of Patent: January 7, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Nobusuke Yamamoto
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Publication number: 20020190352Abstract: A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the &bgr;-crystal structure.Type: ApplicationFiled: January 7, 2002Publication date: December 19, 2002Inventors: Takenobu Kishida, Shinya Tada, Atsushi Ikeda, Takeshi Harada, Kohei Sugihara
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Patent number: RE41866Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (Vth) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si—H chemical bonds at the interface.Type: GrantFiled: June 27, 2001Date of Patent: October 26, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuhiro Yano, Kouichi Mochizuki