Abstract: A power device termination structure is disclosed. The structure comprises a primary field plate electrically connect to a main junction, a secondary field plate electrically connect to a field ring which are apart from the main junction, and a floating field plate formed in between the primary field plate and secondary field plate. The primary field plate and secondary field plate are formed on an insulating layer, and the floating field plate is buried in the insulating layer. The endings of the floating field plate are in alignment with the ends of the extension portion of the primary field plate and the secondary field plate. The primary field plate, the secondary field plate and the floating conductive plate, are capacitively coupled each other so that the electrical field crowding problem is lesser.

Abstract: Apparatus and methods for manufacturing low-resistant substrate contacts in integrated circuits are disclosed. The contacts are low resistive conducting plugs and are located outside the areas of active components. The substrate is connected from the top portion in order to obtain a low resistance. Multiple metal plugs electrically interconnect the substrate of the integrated circuit with the top portion of the integrated circuit.

Abstract: The present invention provides a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide.

Abstract: The first shield pattern is provided between an inductor and the surface of a semiconductor substrate under the inductor. The first shield pattern has plural concave slittings from the side of the edge toward the inside. The second shield pattern provides a convex area which is located on the surface of the semiconductor substrate in correspondence with the slitting wherin metallic silicide is formed and a connection area which is provided on the surface of the semiconductor substrate and in which metallic silicide is formed for connecting plural convex areas.

Abstract: Expansion promotion means (24) for more efficiently promoting the expansion of the depletion layer (19) than the electrically insulating film(14) having a suppressor electrode layer (20) buried therein is arranged between narrow portions (23b) of the suppressor electrode layer to control the expansion of the depletion layer (19), by which arrangement the spacing s between the narrow portions (23b) can be reduced without decreasing the field reducing effect of the field reduction means, which contains the suppressor electrode layer.

Abstract: The present invention is a ferroelectric memory chip having a memory cell region in which there is provided a plurality of memory cells, each having a ferroelectric capacitor, this ferroelectric memory chip being characterized in that there is formed an electromagnetic wave shield layer, which shields the above-mentioned memory cell region against electromagnetic waves from the outside. The electromagnetic wave shield layer is constituted, for example, from either a conductive layer, or a semiconductor layer, which is provided above and/or below the memory cell region, and preferably is connected so as to constitute the same electric potential. Providing such an electromagnetic wave shield layer eliminates the direct irradiation of electromagnetic waves on a word line, plate line and bit line inside the memory cell region, thus making it possible to prevent a change in a storage state by an unexpected electric field being applied to a ferroelectric capacitor inside a memory cell.

Abstract: An integrated electronic device package includes an enclosing structure and a substrate secured within the enclosing structure. At least one first electrical connector protrudes through a first face of the enclosing structure. At least one integrated circuit chip is included within the enclosing structure. The at least one integrated circuit chip is mechanically connected to the substrate and electrically connected to the at least one first electrical connector. Radio-frequency signals are emitted from the at least one integrated circuit chip. A first radiation absorbing device is disposed within the enclosing structure and between the at least one integrated circuit chip and a second face of the enclosing structure.

Abstract: A power semiconductor device includes a die having a drain contact, a source contact, a primary gate contact, a partitioning region that partitions the source contact, and a secondary gate contact disposed in the partitioning region. A conductive strip is connected to the primary and secondary gate contacts. An insulation layer encloses a segment of the conductive strip. A conductive connecting member includes a metal sheet and a conductive paste. The metal sheet is attached to the source contact via the conductive paste and is formed with a groove to expose the insulation layer from the metal sheet.

Abstract: A MOSFET-based ESD protection structure for use in MOS ICs that is relatively immune to thermal overheating during an ESD event. This immunity is achieved by employing a floating heat sink to dissipate heat generation during the ESD event. The structure includes a semiconductor substrate (e.g., a silicon substrate) of a first conductivity type (typically P-type) with a gate insulation layer (e.g., a gate silicon dioxide layer) thereon. A patterned gate layer (e.g., a patterned polysilicon gate layer) overlies the gate insulation layer. Also included are source and drain regions of a second conductivity type disposed in the semiconductor substrate. The structure further includes a floating heat sink disposed above, and in contact with, the drain region, and an interconnect dielectric layer disposed over the semiconductor substrate, the source region, the patterned gate layer and the drain region.

Abstract: A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

Abstract: The main purpose is to provide a semiconductor device which has a field plate wherein the electric field concentration at a step part can be eliminated and a higher withstanding voltage can be gained.

Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Abstract: Disclosed are a method and apparatus which provide a magnetic shield for integrated circuits containing electromagnetic circuit elements. The shield is formed of a magnetically permeable material, which may be a non-conductive magnetic oxide, and either partially contacts or completely surrounds the integrated circuit.

Abstract: In a semiconductor chip with a planar structure, the width of each corner portion of a peripheral electrode in a diagonal direction of the chip is made almost the same as the width of each straight portion of the peripheral electrode, the peripheral electrode having the same potential as a drain electrode in the periphery of the chip. The corner portion of the peripheral electrode is in the form of a partial annular ring. Degradation of the withstand voltage in the semiconductor device is prevented in the high-temperature and high-humidity conditions.

Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a frequency of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage vth, and hence to enhance the reliability of the transfer or reset of electric charges.

Abstract: A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.

Abstract: A vertical semiconductor component having a semiconductor body of a first conductivity type is described. In a surface region of the semiconductor body, at least one zone of a second conductivity type, opposite to the first conductivity type, is embedded. Regions of the second conductivity type are provided in the semiconductor body in a plane running substantially parallel to the surface of the surface region. The regions are in this case sufficiently highly doped that they cannot be depleted of charge carriers when a voltage is applied.

Abstract: A protective structure having a plurality of protection regions extending along closed lines arranged inside each other. Each intermediate protective region is tangent to two different adjacent protective regions, at different areas, so as to form a connection in series with the adjacent protective regions. The protective structure can be of resistive material, such as to form a series of resistors, or it can include doped portions alternately of P- and N-type, such as to form a plurality of anti-series arranged diodes. The structure can be made of polycrystalline silicon extending on the substrate surface, or can be integrated (implanted or diffused) inside the substrate.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them. At least one accelerating region of the same conductivity type as the collector region is formed spaced from the pn junction and at a dose higher than that of the collector region. A field plate overlaps the pn junction and the accelerating region. The field plate has an edge portion that extends past the accelerating region. When a voltage of a reverse direction is applied to the pn junction, an electric field becomes concentrated on the accelerating region as well as on the pn junction and on the edge portion of the field plate. This increases an electric field distribution area and thus also increases the breakdown voltage.

Abstract: An article for de-embedding parasitics and/or acting as an on-wafer calibration standard is disclosed. In particular, some articles in accordance with the present invention provide structures on integrated circuits that mitigate the severity of parasitics Furthermore, some articles in accordance with the present invention are well-suited for use with conductive substrates that operate at high frequencies. In an illustrative embodiment, conductive elements are used to construct structures near and/or around the leads on the integrated circuit. When the structures are grounded, the structures function to (at least) partially shield the leads to and from the DUT in a manner that is analogous to stripline, microstrip and coaxial cable. Because the electric fields emanating from the leads terminate in the grounded structure and not in the conductive substrate of the integrated circuit, the severity of the parasitics in the leads in mitigated.

Abstract: Provided is a semiconductor device with a silicide protection structure that prevents the over-etching of a source/drain layer in forming a contact hole and prevents a voltage drop in surge voltage without increasing the area of the source/drain layer, as well as a manufacturing method of the device. There is defined an active region (AR) of an MOS transistor and a gate electrode (10) that constitutes a field-shield isolation structure is formed in a rectangular loop shape. Over the FS gate electrode (10) and the active region (AR), a gate electrode (20) of the MOS transistor is formed so as to divide the FS gate electrode (10) into two. Each of active regions (AR) facing with each other across the gate electrode (20) has a silicide protection structure (PS1), whose surrounding is an S/D layer (30), and a silicide film (SF1) is formed over the structure (PS1).

Abstract: An integrated circuit is disclosed that comprises structures that confine, shield and/or manipulate the electric fields generated within the integrated circuit so as to improve the performance of the integrated circuit. Such structures include, but are not limited to, transmission lines, capacitors, inductors, filters, and couplers. Although embodiments of the present invention are advantageous for use on many integrated circuits, they are particularly well suited for use with integrated circuits that are disposed on conductive substrates and that operate at high frequencies.

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

Abstract: A structure (and method) for selectively making an electrical connection comprising a conductive element, wherein the conductive element becomes non-conductive after application of radiation energy, and a reflective element, positioned adjacent at least two sides of the conductive element for reflecting the radiation energy.

Abstract: A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.

Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505 . . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .

Abstract: A field shield isolated transistor is provided wherein the left-hand edge (E1) of a left-hand contact pad (51a) is positioned a distance (d5) to the right of the left-hand edge (F1) of a left-hand field shield gate electrode (41); the right-hand edge (E2) of the left-hand contact pad (51a) is positioned a distance (d6) to the right of the right-hand edge (F2) of the left-hand field shield gate electrode (41); the left-hand edge (E3) of a right-hand contact pad (52a) is positioned a distance (d7) to the left of the left-hand edge (F3) of a right-hand field shield gate electrode (42); and the right-hand edge (E4) of the right-hand contact pad (52a) is positioned a distance (d8) to the left of the right-hand edge (F4) of the right-hand field shield gate electrode (42).

Abstract: A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

Abstract: A method of fabricating a semiconductor device, comprises the steps of forming a trench in a semiconductor substrate by using a selective etching process; forming an insulating layer at least on the inner surface of the trench; forming a film containing silicon at least on the insulation layer in the trench and doping a first impurity of a first conductivity type by a first ion implantation to a predetermined depth of the semiconductor substrate at least through the film containing silicon, and wherein the first impurity doped into the semiconductor substrate by the first ion implantation is at a level deeper than the bottom of the trench.

Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.

Abstract: First and second semiconductor devices are separated by a field oxide on a semiconductor substrate, and a field plate is positioned over the field oxide. A leakage detector detects a field leakage current between the first and second semiconductor devices. A field plate generator tunes a potential of said field plate according to a magnitude of the field current detected by the leakage current detector. In this manner, field leakage is optimized, and total dose effects may be monitored for signs of device failure.

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505. . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .

Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.

Abstract: A high voltage semiconductor device having an improved junction termination extension for increasing the surface breakdown junction voltage. The device comprises a semiconductor substrate (10) of a first electrical conductivity type having a major surface (24) with an edge (26). The substrate has a first impurity region (22) of a second electrical conductivity type formed therein and having a first doping concentration and a second impurity region (28) of a said second electrical conductivity type, having a second doping concentration less than the first doping concentration, formed in the substrate between the first impurity region and the edge, and a field shield plate (30) disposed on the major surface in conductive relation with the first impurity region. The first field shield plate has an outer edge which terminates above the second impurity region.

Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (V.sub.th) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si--H chemical bonds at the interface.

Abstract: A diode includes a semiconductor substrate of first conductivity type and including a surface having a doped portion of second conductivity type opposite the first conductivity type. In addition, a dielectric layer on the surface of the substrate extends over a first portion of the doped surface portion and leaves a second portion of the doped surface portion exposed. This dielectric layer includes a low-angle tapered portion having a thickness which increases as said tapered portion extends from the exposed doped surface portion of the substrate. In particular, the low-angle tapered portion of the dielectric layer may extend from the exposed portion of a surface at an angle of less than about 10.degree.. Furthermore, the diode may also include a conductive contact on the exposed portion of the substrate and a field plate extending from the conductive contact over a portion of the dielectric layer.

Abstract: A semiconductor fabrication process for forming a shield-plate electrode or a gate electrode in a trench to have the same conductivity type with each of adjacent p- and n-well regions includes steps for forming a trench in a semiconductor substrate by using a silicon nitride mask, forming an oxide film on the bottom of the trench, and filling a polysilicon film on the oxide film. In a selected region, outside the trench, an impurity of a desired conductivity type is doped by ion implantation to a predetermined depth of the semiconductor substrate. An impurity of the same conductivity type is further doped into the polysilicon film by shallowing the implantation level. In the adjacent region, an impurity of the opposite conductivity type is also doped into the polysilicon film and the semiconductor substrate outside the trench at different implantation levels.

Abstract: Burst pressure P of an insulating layer positioned immediately on a fuse layer is defined by using planar width W of fuse layer and thickness t of insulating layer. The value of the planar width W of fuse layer and the value of the thickness t of insulating layer are set such that the value of burst pressure P is at most about 1000 kg/cm.sup.2. The value of the thickness t and the value of the planar width W are set such that the value t/W is at least 0.45 and at most 0.91. Consequently, stable fuse blowing becomes possible while reducing manufacturing cost.

Abstract: In a MOSFET or other high voltage device, an annular channel stopper (4) extends around the outer periphery (14) of a body portion (11) with which a device region (15) forms a p-n junction (5) operable under high reverse bias in at least one mode of operation of the device. A field plate structure (34, 34a, 34b, 34c) on an insulating layer (24) over the body portion (11) extends towards the outer periphery (14) to spread a depletion layer from the reverse-biased p-n junction (5) towards the outer periphery (14). The channel stopper (4) comprises concentrically doped stopper regions (41 to 44) with different doping concentrations and/or region widths and/or spacings, giving to the body portion (11) a non-uniform doping profile the doping of which, under the field plate structure (34, 34a, 34b, 34c), increases with distance (D) towards the outer periphery (14) to slow progressively the spread of the depletion layer under the field plate structure (34, 34a, 34b, 34c).

Abstract: The semiconductor device includes a silicon substrate, field effect transistors, a flash memory and a separating portion. A plurality of field effect transistors are formed on semiconductor substrate. A flash memory is formed on semiconductor substrate. Separating portion includes a separation electrode. Separating portion electrically separates the plurality of field effect transistors from each other. Separating portion is formed insulated on silicon substrate. Flash memory includes a floating gate electrode and a control gate electrode. Floating gate electrode is formed insulated on silicon substrate. Control gate electrode is formed insulated on floating gate electrode. Separation electrode and floating gate electrode have approximately the same thickness.

Abstract: In an integrated switching circuit with a CMOS circuit and a method for producing isolated active regions of the CMOS circuit, a field plate is doped jointly with wells located beneath it, so that the field plate includes an n-doped region and a p-doped region, and a boundary layer forms in a transition region. Upon electrical connection of the field plate regions with the particular well located beneath them, a flat band condition prevails at a substrate surface.

Abstract: A semiconductor device comprises a semiconductor substrate having N- and P-channel regions formed therein; a plurality of first transistors formed in the N-channel region; a first field shield element-isolation structure having a first shield plate electrode and formed in the N-channel region for isolating the first transistors from each other; a plurality of second transistors formed in the P-channel region; and a second field shield element-isolation structure having a second shield plate electrode electrically connected to the first shield plate electrode and formed in the P-channel region for isolating the second transistors from each other; wherein respective values of a threshold voltage V.sub.tN of a parasitic transistor formed in a field region of the N-channel region, a threshold voltage V.sub.tP of a parasitic transistor formed in a field region of the P-channel region and a potential V.sub.sP of the first or second shield plate electrode are determined so as to meet V.sub.tN -V.sub.tP >V.sub.

Abstract: A semiconductor device equipped on the same substrate thereof with a first area isolated for device isolation by a first device isolation structure and with a second area isolated for device isolation by a second device isolation structure, wherein the thickness of the substrate inside the first area is different from the thickness of the substrate inside the second area, and the first and second device isolation structures are buried into the substrate so as to bring their tops into about the same level.

Abstract: A highly reliable semiconductor device having a planar junction, which comprises a main junction and a plurality of field limiting ring regions surrounding the main junction, and an electrically floating conductive layer to completely cover that part of the surface of an n.sup.- layer between the main junction and the nearest field limiting ring region thereto through an insulating layer to suppress influences by external factors such as charged particles, etc. In accordance with such a structured device, when a voltage for making the main junction into a reverse bias state is applied, the potential of the conductive layer becomes fixed to an intermediate potential between the main junction and the nearest field limiting ring region thereto and plays a role of shield effect. In fact, even if the device is incorporated into a resin-sealed package and subjected to reliability tests (high temperature DC reverse bias tests), the breakdown voltage is not changed at all.

Abstract: Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith.

Abstract: A method is described for fabricating field effect transistors (FETs) having double silicide gate electrodes and interconnecting lines for CMOS circuits. The method reduces the IR voltage drops and RC time delay constants, and thereby improves circuit performance. The method consists of forming FETs having gate electrodes and interconnecting lines from a multilayer made up of a doped first polysilicon layer, a first silicide layer (WSi.sub.2), and a doped second polysilicon layer. After patterning the multilayer to form the gate electrodes, a titanium (Ti) metal is deposited and annealed to form a second silicide layer on the gate electrodes, and simultaneously forms self-aligned Ti silicide contacts on the source/drain areas. The latitude in overetching the contact openings in an insulating (PMD) layer to the gate electrodes extending over the field oxide area is increased, and the contact resistance (R.sub.c) is reduced because of the presence of the WSi.sub.