Abstract: A flexible touch control display module includes an array substrate, an organic light emitting diode (OLED) light emitting layer, a thin film encapsulation layer, a touch control layer, and a polarizing film layer. The polarizing film layer includes an adhesive layer, a photo alignment layer, and a protective layer. The photo alignment layer is disposed on the touch control layer, and the adhesive layer is disposed between the touch control layer and the photo alignment layer, such that the photo alignment layer is adhered to the touch control layer, and the protective layer is disposed on the photo alignment layer.

Abstract: An aluminum-free borosilicate glass includes the following glass composition (in weight-% on oxide basis): 70-80 SiO2; 8-14 B2O3; 0 Al2O3; 0-4 Na2O; 3-10 K2O; 0 Li2O; 3-14 sum Na2O+K2O; 0-1 CaO; 0-1 MgO; 0-1 BaO; 0-1 SrO; 0-2 sum CaO+MgO+BaO+SrO; 0-1 ZnO; 3.6-14 ZrO2; 0-10 TiO2; and 0.01-2.0 one or more refining agents, the weight ratio of ZrO2:K2O being in a range of 1.2:1 to 1.4:1.

Abstract: A method of making a semiconductor package structure includes bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies. The method further includes adhering a first stress relief structure to the substrate at a corner of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method further includes adhering a second stress relief structure to the substrate along a single edge of the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.

Abstract: An SOI substrate is attracted to and detached from an electrostatic chuck included in a semiconductor manufacturing device without failures. A semiconductor device includes a semiconductor substrate made of silicon, a first insulating film formed on a main surface of the semiconductor substrate and configured to generate compression stress to silicon, a waveguide, made of silicon, formed on the first insulating film, and a first interlayer insulating film formed on the first insulating film so as to cover the waveguide. Further, a second insulating film configured to generate tensile stress to silicon is formed on the first interlayer insulating film and in a region distant from the optical waveguide by a thickness of the first insulating film or larger. The second insulating film offsets the compression of the first insulating film.

Abstract: An adhesive, and an encapsulated product and method of encapsulating an organic electronic device (OED) using the same are provided. The adhesive film serves to encapsulate the OED and includes a curable resin and a moisture absorbent, and the adhesive includes a first region coming in contact with the OED upon encapsulation of the OED and a second region not coming in contact with the OED. Also, the moisture absorbent is present at contents of 0 to 20% and 80 to 100% in the first and second regions, respectively, based on the total weight of the moisture absorbent in the adhesive.

Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.

Abstract: An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.

Abstract: Disclosed herein is a thermally-assisted magnetic tunnel junction structure including a thermal barrier. The thermal barrier is composed of a cermet material in a disordered form such that the thermal barrier has a low thermal conductivity and a high electric conductivity. Compared to conventional magnetic tunnel junction structures, the disclosed structure can be switched faster and has improved compatibility with standard semiconductor fabrication processes.

Abstract: An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature.

Abstract: A semiconductor device includes a semiconductor substrate; an insulating film arranged on the semiconductor substrate; an electrode that contacts a portion of a side surface of the insulating film; a first passivation film that is arranged extending from the electrode to the insulating film, and contacts a surface of the insulating film, and contacts a surface of the electrode; and a second passivation film that is arranged on the first passivation film. A difference between a linear expansion coefficient of the first passivation film and a linear expansion coefficient of the insulating film is smaller than a difference between the linear expansion coefficient of the first passivation film and a linear expansion coefficient of the electrode, and a position where the first passivation film contacts a boundary between the electrode and the insulating film is positioned lower than an upper surface of the insulating film.

Abstract: A light-emitting device includes a substrate, a plurality of light-emitting elements mounted on one surface of the substrate, a first glass film provided to one surface of the substrate and having a plurality of apertures that form a light-reflecting frame surrounding the perimeter of each the light-emitting elements, and a second glass film provided to the other surface of the substrate. A coefficient of thermal expansion of the second glass film is greater than that of the substrate when a coefficient of thermal expansion of the first glass film is greater than that of the substrate, and a coefficient of thermal expansion of the second glass film is less than that of the substrate when a coefficient of thermal expansion of the first glass film is less than that of the substrate.

Abstract: A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.

Abstract: A glass to be used in a scattering layer of an organic LED element, and an organic LED element using the scattering layer are provided. The organic LED element of the present invention includes, a transparent substrate, a first electrode provided on the transparent electrode, an organic layer provided on the first electrode, and a second electrode provided on the organic layer, and further includes a scattering layer including, in terms of mol % on the basis of oxides, 15 to 30% of P2O5, 5 to 25% of Bi2O3, 5 to 27% of Nb2O5, and 10 to 35% of ZnO and having a total content of alkali metal oxides including Li2O, Na2O and K2O of 5% by mass or less.

Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.

Abstract: On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.

Abstract: A packaging substrate structure with a semiconductor chip embedded therein is disclosed, including a carrier board having a first and an opposed second surfaces and disposed with at least a through cavity; a semiconductor chip received in the through cavity, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is disposed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are disposed on surfaces of the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures disposed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expa

Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion layer, and having projections and depressions on a surface thereof opposing to the first substrate, the projections and depressions having rounded tips and bottoms; active elements provided on the thin glass layer, each active element corresponding to a pixel; a display provided above the thin glass layer, and driven by the active elements to display an image pixel by pixel; and a second substrate provided on the display, and having an opposing electrode formed thereon.

Abstract: Disclosed is a semiconductor device having a wafer level package structure which is characterized by containing a resin layer composed of a resin composition which is curable at 250° C. or less. Such a semiconductor device having a wafer level package structure is excellent in low stress properties, solvent resistance, low water absorbency, electrical insulation properties, adhesiveness and the like.

Abstract: On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.

Abstract: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion layer, and having projections and depressions on a surface thereof opposing to the first substrate, the projections and depressions having rounded tips and bottoms; active elements provided on the thin glass layer, each active element corresponding to a pixel; a display provided above the thin glass layer, and driven by the active elements to display an image pixel by pixel; and a second substrate provided on the display, and having an opposing electrode formed thereon.

Abstract: A thermal treatment apparatus, a method for manufacturing a semiconductor device, and a method for manufacturing a substrate, wherein the occurrence of slip dislocation in a substrate during heat treatment is reduced, and a high-quality semiconductor device can be manufactured, are intended to be provided. A substrate support 30 is formed from a main body portion 56 and a supporting portion 58. In the main body portion 56, a plurality of placing portions 66 extend parallel, and supporting portions 58 are provided on the placing portions 66. A substrate 68 is placed on the supporting portion 58. The supporting portion 58 has a smaller area than an area of a flat face of the substrate, and is formed from a silicon plate having a thickness larger than thickness of the substrate, so that deformation during heat treatment is reduced. The supporting portion 58 is made of silicon, and a layer coated with silicon carbide (SiC) is formed on a substrate-placing face of the supporting portion 58.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A method of manufacturing a thermoelectric module is provided. The method includes mounting a thermoelectric material to a substrate such that a portion of the thermoelectric material covers a removable pattern. The thermoelectric material is then segmented and the removable pattern is removed. The portions of the thermoelectric material which were covering the removable pattern are also removed, leaving the portions of the thermoelectric material not covering the removable pattern attached to the substrate.

Abstract: A principal surface at one side of a support substrate has thereon an adjustment layer made of material having a higher thermal expansion coefficient than that of the support substrate. Then, a nitride-base semiconductor element layer and the support substrate on a growth substrate are joined via an adhesion layer. Next, the support substrate is joined to the nitride-base semiconductor element layer via the adhesion layer. Next, the growth substrate is separated from the joined nitride-base semiconductor element layer and the support substrate.

Abstract: There is described a method for creating a thermally-isolated microstructure on a slab of mono-crystalline silicon which uses a hybrid dry-then-wet etch technique that when controlled, can produce microstructures without any silicon adhering underneath, microstructures having small masses of silicon adhering underneath, and microstructures that are still attached to the slab of mono-crystalline silicon via a waisted silicon body. When creating the microstructures with a waisted silicon body, the thermal isolation of the microstructure can be designed by controlling the depth of the etching and the size of the waist.

Abstract: In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit formed from silicon located on a sapphire substrate, and a thick passivation layer. The electronic devices may be implemented in the context of hydrocarbon drilling and production operations.

Abstract: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

Abstract: A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for contacting and providing electrical connectivity to a plurality of contact pads of a superordinate circuit board. At least one of the two limb ends is electrically connected to the contact areas of a semiconductor chip, while the other limb end is elastically supported on the top side of the semiconductor chip, thereby enabling the connecting element to be self supporting.

Abstract: A process for producing doped semiconductor wafers from silicon, which contain an electrically active dopant, such as boron, phosphorus, arsenic or antimony, optionally are additionally doped with germanium and have a defined thermal conductivity, involves producing a single crystal from silicon and processing further to form semiconductor wafers, the thermal conductivity being established by selecting a concentration of the electrically active dopant and optionally a concentration of germanium. Semiconductor wafers produced from silicon by the process have specific properties with regard to thermal conductivity and resistivity.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.

Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.

Abstract: Improved method of heat-treating a glass substrate, especially where the substrate is thermally treated (such as formation of films, growth of films, and oxidation) around or above its strain point. If devices generating heat are formed on the substrate, it dissipates the heat well. An aluminum nitride film is formed on at least one surface of the substrate. This aluminum nitride film acts as a heat sink and prevents local concentration of heat produced by the devices such as TFTs formed on the glass substrate surface.

Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

Abstract: A SnO2 ISFET device and manufacturing method thereof. The present invention prepares SnO2 as the detection membrane of an ISFET by sol-gel technology to obtain a SnO2 ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the SnO2 ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rate of the SnO2 ISFET for different pH and hysteresis width of the SnO2 ISFET for different pH loop are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the SnO2 ISFET.

Abstract: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention use materials with superior thermo-mechanical properties, in particular, the Coefficient of Thermal Expansion (CTE), melting temperature, tensile strength and fracture toughness. The thermo-mechanical energy absorber materials are incorporated in, or replace, components of the ESD device that are susceptible to thermo-mechanical stress and cracking due to localized heating and thermal expansion.

Abstract: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion layer, and having projections and depressions on a surface thereof opposing to the first substrate, the projections and depressions having rounded tips and bottoms; active elements provided on the thin glass layer, each active element corresponding to a pixel; a display provided above the thin glass layer, and driven by the active elements to display an image pixel by pixel; and a second substrate provided on the display, and having an opposing electrode formed thereon.

Abstract: A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.

Abstract: An organic electro-luminescent display device and a method of fabricating the same are disclosed in the present invention. The organic electro-luminescent display device includes a plurality of pixels on a substrate, a thin film transistor coupled to each pixel, an organic electro-luminescent device coupled to the thin film transistor, a packaging layer on the organic electro-luminescent device, wherein the packaging layer comprises first and second inorganic layers having opposite stresses, and a first organic layer between the first and second inorganic layers.

Abstract: Improved method of heat-treating a glass substrate, especially where the substrate is thermally treated (such as formation of films, growth of films, and oxidation) around or above its strain point If devices generating heat are formed on the substrate, it dissipates the heat well. An aluminum nitride film is formed on at least one surface of the substrate. This aluminum nitride film acts as a heat sink and prevents local concentration of heat produced by the devices such as TFTs formed on the glass substrate surface.

Abstract: A superlattice thermoelectric device. The device includes p-legs and n-legs, each leg includes a large number of at least two different very thin alternating layers of elements. The n-legs in the device includes alternating layers of silicon and silicon carbide. In preferred embodiments p-legs include a superlatice of B-C layers, with alternating layers of different stoichiometric forms of B-C. This preferred embodiment is designed to produce 20 Watts with a temperature difference of 300 degrees C. with a module efficiency of about 30 percent. The module is about 1 cm thick with a cross section area of about 7 cm2 and has about 10,000 sets of n and p legs each set of legs being about 55 microns thick and having about 5,000 very thin layers (each layer about 10 nm thick).

Abstract: A method for manufacturing an integrated circuit on a semiconductor wafer is provided. The semiconductor wafer has complete die and partial die areas thereon. Functional circuit patterns are formed in a plurality of the complete die areas. The thermal absorption properties of the semiconductor wafer are tuned by forming differing patterns in a plurality of the partial die areas.

Abstract: The present invention provides two or more test structures/substructures (100) that are used in a test pattern (500, 600, 700, 800) to determine a cracking threshold for a dielectric material (104) on a substrate. Each test structure/substructure (100) includes two metal structures (102) separated by the dielectric material (104) having a width (G) which is different for each test structure/substructure (100). The cracking threshold will be approximately equal to the largest width (G) of dielectric material (104) that is cracked after processing. The present invention also provides a method for determining the cracking threshold for the dielectric material (104). Two or more test structures (100) are formed on the substrate (402) followed by a determination of whether the dielectric material (104) between the two metal structures (102) for each test structure (100) has cracked during processing (404).

Abstract: The aluminum-free borosilicate glass has a composition in percent by weight based on oxide content of: SiO2, 65-77; B2O3, 7-20; Li2O, 0-2; Na2O, 0-4; K2O, 3-12; MgO, 0-2; CaO, 0-2; with MgO+CaO, 0-3; BaO, 0-3; ZnO, 0-2; ZrO2, 0.8-12; TiO2, 0-10; CeO2, 0-1; and F−, 0-0.6. This glass advantageously has a coefficient of thermal expansion &agr; (20° C.; 300° C.) of between 3.0×10−6/K and 6×10−6/K, good chemical resistance and a working point VA of between 990° C. and 1290° C.

Abstract: A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing a second carrier gas at a second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate. The second carrier gas flow rate is greater than the first carrier gas flow rate.